"A 4-bit 4.5-ns-Latency Pseudo-ReRAM Computing-In-Memory Macro With Self ..."

Jongho Kim et al. (2023)

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DOI: 10.1109/TCSII.2023.3273290

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type: Journal Article

metadata version: 2023-09-14

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Jongho Kim, Young H. Oh, Hyeonsik Kim, Jae W. Lee, Jintae Kim:
A 4-bit 4.5-ns-Latency Pseudo-ReRAM Computing-In-Memory Macro With Self Error-Correcting DTC-Based WL Drivers and 6-bit CDAC-Less Column ADCs Having Ultra-Narrow Pitch. IEEE Trans. Circuits Syst. II Express Briefs 70(9): 3228-3232 (2023)

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