"Low-Power, High-Speed, and Area-Efficient Multiplier Based on the PTL ..."

Wanyuan Pan et al. (2024)

> Home

Details and statistics

DOI: 10.1109/TCSII.2024.3366169

access: closed

type: Journal Article

metadata version: 2024-07-19

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcasII/PanYTYY24
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcasII/PanYTYY24
Wanyuan Pan, Yihe Yu, Chengcheng Tang, Ningyuan Yin, Zhiyi Yu:
Low-Power, High-Speed, and Area-Efficient Multiplier Based on the PTL Logic Style. IEEE Trans. Circuits Syst. II Express Briefs 71(7): 3538-3542 (2024)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.