"An Efficient and Parallelism-Scalable Large Integer Multiplier ..."

Jianfei Wang et al. (2025)

> Home

Details and statistics

DOI: 10.1109/TCSII.2024.3457494

access: closed

type: Journal Article

metadata version: 2025-03-06

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcasII/WangHZMSY25
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcasII/WangHZMSY25
Jianfei Wang, Jia Hou, Fahong Zhang, Yishuo Meng, Yang Su, Chen Yang:
An Efficient and Parallelism-Scalable Large Integer Multiplier Architecture Using Least-Positive Form and Winograd Fast Algorithm. IEEE Trans. Circuits Syst. II Express Briefs 72(1): 248-252 (2025)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.