"A 28nm 32Kb SRAM Computing-in-Memory Macro With Hierarchical Capacity ..."

Kanglin Xiao et al. (2023)

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DOI: 10.1109/TCSII.2023.3234620

access: closed

type: Journal Article

metadata version: 2023-06-15

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Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Jiahao Song, Haoyang Luo, Xin'an Wang, Yuan Wang:
A 28nm 32Kb SRAM Computing-in-Memory Macro With Hierarchical Capacity Attenuator and Input Sparsity-Optimized ADC for 4b Mac Operation. IEEE Trans. Circuits Syst. II Express Briefs 70(6): 1816-1820 (2023)

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