"An area-efficient pipelined VLSI architecture for decoding of Reed-Solomon ..."

Jah-Ming Hsu, Chin-Liang Wang (1997)

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DOI: 10.1109/76.644066

access: closed

type: Journal Article

metadata version: 2020-08-25

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Jah-Ming Hsu, Chin-Liang Wang:
An area-efficient pipelined VLSI architecture for decoding of Reed-Solomon codes based on a time-domain algorithm. IEEE Trans. Circuits Syst. Video Technol. 7(6): 864-871 (1997)

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