"A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors."

Gabriel Torrens et al. (2019)

> Home

Details and statistics

DOI: 10.1109/TETC.2017.2721932

access: closed

type: Journal Article

metadata version: 2022-10-02

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tetc/TorrensACMSB19
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tetc/TorrensACMSB19
Gabriel Torrens, Bartomeu Alorda, Cristian Carmona, Daniel Malagón-Periánez, Jaume Segura, Sebastià A. Bota:
A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors. IEEE Trans. Emerg. Top. Comput. 7(3): 447-455 (2019)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.