"A Hardware Accelerator and FPGA Realization for Reduced Visibility Graph ..."

K. Sridharan, T. K. Priya (2007)

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DOI: 10.1109/TIE.2007.894726

access: closed

type: Journal Article

metadata version: 2020-05-22

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K. Sridharan, T. K. Priya:
A Hardware Accelerator and FPGA Realization for Reduced Visibility Graph Construction Using Efficient Bit Representations. IEEE Trans. Ind. Electron. 54(3): 1800-1804 (2007)

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