"Real-Time Visual Saliency Architecture for FPGA With Top-Down Attention ..."

Francisco Barranco et al. (2014)

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DOI: 10.1109/TII.2014.2319581

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type: Journal Article

metadata version: 2020-11-10

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Francisco Barranco, Javier Díaz, Begoña del Pino, Eduardo Ros:
Real-Time Visual Saliency Architecture for FPGA With Top-Down Attention Modulation. IEEE Trans. Ind. Informatics 10(3): 1726-1735 (2014)

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