"Analysis and efficient implementation of IEEE-754 decimal floating point ..."

Marcelo Tosini, Martín Vázquez, Lucas Leiva (2024)

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DOI: 10.1007/S11227-023-05808-W

access: closed

type: Journal Article

metadata version: 2024-05-07

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Marcelo Tosini, Martín Vázquez, Lucas Leiva:
Analysis and efficient implementation of IEEE-754 decimal floating point adders/subtractors in FPGAs for DPD and BID encoding. J. Supercomput. 80(7): 9298-9326 (2024)

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