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"A 6.0-GS/s Time-Interleaved DAC Using an Asymmetric Current-Tree Summation ..."

Yushen Fu et al. (2023)

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DOI: 10.1109/TVLSI.2022.3232516

access: closed

type: Journal Article

metadata version: 2023-02-10

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Yushen Fu, Chengyu Huang, Limeng Sun, Weiguang Meng, Xueqing Li, Huazhong Yang:
A 6.0-GS/s Time-Interleaved DAC Using an Asymmetric Current-Tree Summation Network and Differential Clock Timing Calibration. IEEE Trans. Very Large Scale Integr. Syst. 31(2): 199-209 (2023)

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