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"A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, ..."

Fazal Hameed, Jerónimo Castrillón (2019)

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DOI: 10.1109/TVLSI.2019.2918385

access: closed

type: Journal Article

metadata version: 2020-03-11

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  - https://dblp.org/rec/journals/tvlsi/HameedC19
Fazal Hameed, Jerónimo Castrillón:
A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement. IEEE Trans. Very Large Scale Integr. Syst. 27(10): 2375-2386 (2019)

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