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"Petri net modeling of gate and interconnect delays for power estimation."

Ashok K. Murugavel, N. Ranganathan (2003)

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DOI: 10.1109/TVLSI.2003.817110

access: closed

type: Journal Article

metadata version: 2020-03-11

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Ashok K. Murugavel, N. Ranganathan:
Petri net modeling of gate and interconnect delays for power estimation. IEEE Trans. Very Large Scale Integr. Syst. 11(5): 921-927 (2003)

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