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"Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained ..."

Juan Núñez, Maria J. Avedillo, José M. Quintana (2014)

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DOI: 10.1109/TVLSI.2013.2283306

access: closed

type: Journal Article

metadata version: 2020-03-11

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  - journals/tvlsi/NunezAQ14
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  - https://dblp.org/rec/journals/tvlsi/NunezAQ14
Juan Núñez, Maria J. Avedillo, José M. Quintana:
Experimental Validation of a Two-Phase Clock Scheme for Fine-Grained Pipelined Circuits Based on Monostable to Bistable Logic Elements. IEEE Trans. Very Large Scale Integr. Syst. 22(10): 2238-2242 (2014)

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