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"A Fault Tolerance Technique for Combinational Circuits Based on ..."

Ahmad T. Sheikh et al. (2017)

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DOI: 10.1109/TVLSI.2016.2569532

access: closed

type: Journal Article

metadata version: 2021-10-14

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Ahmad T. Sheikh, Aiman H. El-Maleh, Muhammad E. S. Elrabaa, Sadiq M. Sait:
A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 224-237 (2017)

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