default search action
"An 8.55-17.11-GHz DDS FMCW Chirp Synthesizer PLL Based on Double-Edge ..."
Jinhai Xiao et al. (2022)
- Jinhai Xiao, Ning Liang, Bingwen Chen, Maliang Liu:
An 8.55-17.11-GHz DDS FMCW Chirp Synthesizer PLL Based on Double-Edge Zero-Crossing Sampling PD With 51.7-fsrms Jitter and Fast Frequency Hopping. IEEE Trans. Very Large Scale Integr. Syst. 30(3): 267-276 (2022)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.