"High-performance VLSI multiplier with a new redundant binary coding."

Xiaoping Huang et al. (1991)

> Home

Details and statistics

DOI: 10.1007/BF00936901

access: closed

type: Journal Article

metadata version: 2020-05-20

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/vlsisp/HuangWCM91
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/vlsisp/HuangWCM91
Xiaoping Huang, Belle W. Y. Wei, Honglu Chen, Yuhai H. Mao:
High-performance VLSI multiplier with a new redundant binary coding. J. VLSI Signal Process. 3(4): 283-291 (1991)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.