"A Low Power Approach to Floating Point Adder Design for DSP Applications."

R. V. K. Pillai et al. (2001)

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DOI: 10.1023/A:1008140025773

access: closed

type: Journal Article

metadata version: 2020-05-20

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R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili, S. Y. A. Shah:
A Low Power Approach to Floating Point Adder Design for DSP Applications. J. VLSI Signal Process. 27(3): 195-213 (2001)

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