"Modified Binary Multiplier Architecture to Achieve Reduced Latency and ..."

Geetam Singh Tomar, Marcus Lloyde George (2018)

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DOI: 10.1007/S11277-017-5028-Z

access: closed

type: Journal Article

metadata version: 2020-12-29

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Geetam Singh Tomar, Marcus Lloyde George:
Modified Binary Multiplier Architecture to Achieve Reduced Latency and Hardware Utilization. Wirel. Pers. Commun. 98(4): 3549-3561 (2018)

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