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"Formal Specification and Verification of Security Mechanisms for RISC-V ..."
- Matthieu Baty:

Formal Specification and Verification of Security Mechanisms for RISC-V Processors: Non-final version. (Spécification et vérification formelle de mécanismes de sécurité pour processeurs RISC-V / Spécification et vérification formelle de mécanismes de sécurité pour processeurs RISC-V: Version non-finale). CentraleSupélec, Châtenay-Malabry, France, 2024

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