"Logic Synthesis with AND and OR Gates in Multi-levels."

Yuichi Nakamura, Saburo Muroga (1999)

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DOI: 10.1201/9781420049671.CH29

access: closed

type: Reference Work

metadata version: 2023-03-10

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Yuichi Nakamura, Saburo Muroga:
Logic Synthesis with AND and OR Gates in Multi-levels. The VLSI Handbook 1999

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