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@article{DBLP:journals/thipeac/BijlsmaBS19,
  author    = {Tjerk Bijlsma and
               Marco Jan Gerrit Bekooij and
               Gerard J. M. Smit},
  title     = {Circular Buffers with Multiple Overlapping Windows for Cyclic Task
               Graphs},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {5},
  pages     = {39--58},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-3-662-58834-5\_3},
  doi       = {10.1007/978-3-662-58834-5\_3},
  timestamp = {Fri, 06 Mar 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/journals/thipeac/BijlsmaBS19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/CarpenterRA19,
  author    = {Paul M. Carpenter and
               Alex Ram{\'{\i}}rez and
               Eduard Ayguad{\'{e}}},
  title     = {The Abstract Streaming Machine: Compile-Time Performance Modelling
               of Stream Programs on Heterogeneous Multiprocessors},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {5},
  pages     = {79--99},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-3-662-58834-5\_5},
  doi       = {10.1007/978-3-662-58834-5\_5},
  timestamp = {Fri, 06 Mar 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/journals/thipeac/CarpenterRA19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/FerreiraBLPC19,
  author    = {Ricardo S. Ferreira and
               Cristoferson Bueno and
               Marcone Laure and
               Monica Magalh{\~{a}}es Pereira and
               Luigi Carro},
  title     = {A Dynamic Reconfigurable Super-VLIW Architecture for a Fault Tolerant
               Nanoscale Design},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {5},
  pages     = {121--139},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-3-662-58834-5\_7},
  doi       = {10.1007/978-3-662-58834-5\_7},
  timestamp = {Fri, 06 Mar 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/journals/thipeac/FerreiraBLPC19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/GenserBSWH19,
  author    = {Andreas Genser and
               Christian Bachmann and
               Christian Steger and
               Reinhold Weiss and
               Josef Haid},
  title     = {A Hardware-Accelerated Estimation-Based Power Profiling Unit - Enabling
               Early Power-Aware Embedded Software Design and On-Chip Power Management},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {5},
  pages     = {59--78},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-3-662-58834-5\_4},
  doi       = {10.1007/978-3-662-58834-5\_4},
  timestamp = {Fri, 06 Mar 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/journals/thipeac/GenserBSWH19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/KalokerinosPNKY19,
  author    = {George Kalokerinos and
               Vassilis Papaefstathiou and
               George Nikiforos and
               Stamatis G. Kavadias and
               Xiaojun Yang and
               Dionisios N. Pnevmatikatos and
               Manolis Katevenis},
  title     = {Prototyping a Configurable Cache/Scratchpad Memory with Virtualized
               User-Level {RDMA} Capability},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {5},
  pages     = {100--120},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-3-662-58834-5\_6},
  doi       = {10.1007/978-3-662-58834-5\_6},
  timestamp = {Fri, 06 Mar 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/journals/thipeac/KalokerinosPNKY19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/LamaJKT19,
  author    = {Carlos S. de La Lama and
               Pekka J{\"{a}}{\"{a}}skel{\"{a}}inen and
               Heikki Kultala and
               Jarmo Takala},
  title     = {Programmable and Scalable Architecture for Graphics Processing Units},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {5},
  pages     = {21--38},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-3-662-58834-5\_2},
  doi       = {10.1007/978-3-662-58834-5\_2},
  timestamp = {Fri, 06 Mar 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/journals/thipeac/LamaJKT19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/MembarthDHT19,
  author    = {Richard Membarth and
               Hritam Dutta and
               Frank Hannig and
               J{\"{u}}rgen Teich},
  title     = {Efficient Mapping of Streaming Applications for Image Processing on
               Graphics Cards},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {5},
  pages     = {1--20},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-3-662-58834-5\_1},
  doi       = {10.1007/978-3-662-58834-5\_1},
  timestamp = {Fri, 06 Mar 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/journals/thipeac/MembarthDHT19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:journals/thipeac/2019-5,
  editor    = {Cristina Silvano and
               Koen Bertels and
               Michael J. Schulte},
  title     = {Transactions on High-Performance Embedded Architectures and Compilers
               {V}},
  series    = {Lecture Notes in Computer Science},
  volume    = {11225},
  publisher = {Springer},
  year      = {2019},
  url       = {https://doi.org/10.1007/978-3-662-58834-5},
  doi       = {10.1007/978-3-662-58834-5},
  isbn      = {978-3-662-58833-8},
  timestamp = {Tue, 14 May 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/2019-5.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/AnsariLKJKW11,
  author    = {Mohammad Ansari and
               Mikel Luj{\'{a}}n and
               Christos Kotselidis and
               Kim Jarvis and
               Chris C. Kirkham and
               Ian Watson},
  title     = {Robust Adaptation to Available Parallelism in Transactional Memory
               Applications},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {3},
  pages     = {236--255},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-19448-1\_13},
  doi       = {10.1007/978-3-642-19448-1\_13},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/AnsariLKJKW11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/AnsariLKJKW11a,
  author    = {Mohammad Ansari and
               Mikel Luj{\'{a}}n and
               Christos Kotselidis and
               Kim Jarvis and
               Chris C. Kirkham and
               Ian Watson},
  title     = {Transaction Reordering to Reduce Aborts in Software Transactional
               Memory},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {4},
  pages     = {195--214},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-24568-8\_10},
  doi       = {10.1007/978-3-642-24568-8\_10},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/AnsariLKJKW11a.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/AzevedoJMTHARV11,
  author    = {Arnaldo Azevedo and
               Ben H. H. Juurlink and
               Cor Meenderinck and
               Andrei Sergeevich Terechko and
               Jan Hoogerbrugge and
               Mauricio Alvarez and
               Alex Ram{\'{\i}}rez and
               Mateo Valero},
  title     = {A Highly Scalable Parallel Implementation of {H.264}},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {4},
  pages     = {111--134},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-24568-8\_6},
  doi       = {10.1007/978-3-642-24568-8\_6},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/AzevedoJMTHARV11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/BartoliniFP11,
  author    = {Sandro Bartolini and
               Pierfrancesco Foglia and
               Cosimo Antonio Prete},
  title     = {Eighth {MEDEA} Workshop},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {3},
  pages     = {91--92},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-19448-1\_5},
  doi       = {10.1007/978-3-642-19448-1\_5},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/BartoliniFP11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/BeiuMKM11,
  author    = {Valeriu Beiu and
               Basheer A. M. Madappuram and
               Peter M. Kelly and
               Liam McDaid},
  title     = {On Two-Layer Brain-Inspired Hierarchical Topologies - {A} Rent's Rule
               Approach -},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {4},
  pages     = {311--333},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-24568-8\_16},
  doi       = {10.1007/978-3-642-24568-8\_16},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/BeiuMKM11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/BlumrichSG11,
  author    = {Matthias A. Blumrich and
               Valentina Salapura and
               Alan Gara},
  title     = {Exploring the Architecture of a Stream Register-Based Snoop Filter},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {3},
  pages     = {93--114},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-19448-1\_6},
  doi       = {10.1007/978-3-642-19448-1\_6},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/BlumrichSG11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/CopeCLH11,
  author    = {Ben Cope and
               Peter Y. K. Cheung and
               Wayne Luk and
               Lee W. Howes},
  title     = {A Systematic Design Space Exploration Approach to Customising Multi-Processor
               Architectures: Exemplified Using Graphics Processors},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {4},
  pages     = {63--83},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-24568-8\_4},
  doi       = {10.1007/978-3-642-24568-8\_4},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/CopeCLH11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/DevosCVS11,
  author    = {Harald Devos and
               Jan Van Campenhout and
               Ingrid Verbauwhede and
               Dirk Stroobandt},
  title     = {Constructing Application-Specific Memory Hierarchies on FPGAs},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {3},
  pages     = {201--216},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-19448-1\_11},
  doi       = {10.1007/978-3-642-19448-1\_11},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/DevosCVS11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/GoudarziIN11,
  author    = {Maziar Goudarzi and
               Tohru Ishihara and
               Hamid Noori},
  title     = {Software-Level Instruction-Cache Leakage Reduction Using Value-Dependence
               of {SRAM} Leakage in Nanometer Technologies},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {3},
  pages     = {275--299},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-19448-1\_15},
  doi       = {10.1007/978-3-642-19448-1\_15},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/GoudarziIN11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/HenryN11,
  author    = {Michael B. Henry and
               Leyla Nazhandali},
  title     = {Hybrid Super/Subthreshold Design of a Low Power Scalable-Throughput
               {FFT} Architecture},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {4},
  pages     = {175--194},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-24568-8\_9},
  doi       = {10.1007/978-3-642-24568-8\_9},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/HenryN11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/HoogerbruggeT11,
  author    = {Jan Hoogerbrugge and
               Andrei Sergeevich Terechko},
  title     = {A Multithreaded Multicore System for Embedded Media Processing},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {3},
  pages     = {154--173},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-19448-1\_9},
  doi       = {10.1007/978-3-642-19448-1\_9},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/HoogerbruggeT11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/JaddoeTP11,
  author    = {Stanley Jaddoe and
               Mark Thompson and
               Andy D. Pimentel},
  title     = {Signature-Based Calibration of Analytical Performance Models for System-Level
               Design Space Exploration},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {4},
  pages     = {409--425},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-24568-8\_21},
  doi       = {10.1007/978-3-642-24568-8\_21},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/JaddoeTP11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/JahreN11,
  author    = {Magnus Jahre and
               Lasse Natvig},
  title     = {A High Performance Adaptive Miss Handling Architecture for Chip Multiprocessors},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {4},
  pages     = {1--20},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-24568-8\_1},
  doi       = {10.1007/978-3-642-24568-8\_1},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/JahreN11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/JonesOAG11,
  author    = {Timothy M. Jones and
               Michael F. P. O'Boyle and
               Jaume Abella and
               Antonio Gonz{\'{a}}lez},
  title     = {Compiler Directed Issue Queue Energy Reduction},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {4},
  pages     = {42--62},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-24568-8\_3},
  doi       = {10.1007/978-3-642-24568-8\_3},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/JonesOAG11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/KhanK11,
  author    = {Omer Khan and
               Sandip Kundu},
  title     = {Microvisor: {A} Runtime Architecture for Thermal Management in Chip
               Multiprocessors},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {4},
  pages     = {84--110},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-24568-8\_5},
  doi       = {10.1007/978-3-642-24568-8\_5},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/KhanK11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/KlugOWT11,
  author    = {Tobias Klug and
               Michael Ott and
               Josef Weidendorfer and
               Carsten Trinitis},
  title     = {autopin - Automated Optimization of Thread-to-Core Pinning on Multicore
               Systems},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {3},
  pages     = {219--235},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-19448-1\_12},
  doi       = {10.1007/978-3-642-19448-1\_12},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/KlugOWT11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/KoteraAETK11,
  author    = {Isao Kotera and
               Kenta Abe and
               Ryusuke Egawa and
               Hiroyuki Takizawa and
               Hiroaki Kobayashi},
  title     = {Power-Aware Dynamic Cache Partitioning for CMPs},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {3},
  pages     = {135--153},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-19448-1\_8},
  doi       = {10.1007/978-3-642-19448-1\_8},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/KoteraAETK11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/LatorreMGCG11,
  author    = {Fernando Latorre and
               Grigorios Magklis and
               Jos{\'{e}} Gonz{\'{a}}lez and
               Pedro Chaparro and
               Antonio Gonz{\'{a}}lez},
  title     = {{CROB:} Implementing a Large Instruction Window through Compression},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {3},
  pages     = {115--134},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-19448-1\_7},
  doi       = {10.1007/978-3-642-19448-1\_7},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/LatorreMGCG11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/LiaoJS11,
  author    = {Xiongfei Liao and
               Wu Jigang and
               Thambipillai Srikanthan},
  title     = {A Modular Simulator Framework for Network-on-Chip Based Manycore Chips
               Using {UNISIM}},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {4},
  pages     = {234--253},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-24568-8\_12},
  doi       = {10.1007/978-3-642-24568-8\_12},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/LiaoJS11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/LinC11,
  author    = {Chun{-}Chieh Lin and
               Chuen{-}Liang Chen},
  title     = {Cache Sensitive Code Arrangement for Virtual Machine},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {3},
  pages     = {24--42},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-19448-1\_2},
  doi       = {10.1007/978-3-642-19448-1\_2},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/LinC11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/LlorenteKWH11,
  author    = {Daniel Llorente and
               Kimon Karras and
               Thomas Wild and
               Andreas Herkersdorf},
  title     = {Advanced Packet Segmentation and Buffering Algorithms in Network Processors},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {4},
  pages     = {334--353},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-24568-8\_17},
  doi       = {10.1007/978-3-642-24568-8\_17},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/LlorenteKWH11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/MoretoCRV11,
  author    = {Miquel Moret{\'{o}} and
               Francisco J. Cazorla and
               Alex Ram{\'{\i}}rez and
               Mateo Valero},
  title     = {Dynamic Cache Partitioning Based on the {MLP} of Cache Misses},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {3},
  pages     = {3--23},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-19448-1\_1},
  doi       = {10.1007/978-3-642-19448-1\_1},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/MoretoCRV11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/MuralidharaK11,
  author    = {Sai Prashanth Muralidhara and
               Mahmut T. Kandemir},
  title     = {Communication Based Proactive Link Power Management},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {4},
  pages     = {135--154},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-24568-8\_7},
  doi       = {10.1007/978-3-642-24568-8\_7},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/MuralidharaK11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/OsborneLCM11,
  author    = {William George Osborne and
               Wayne Luk and
               Jos{\'{e}} Gabriel F. Coutinho and
               Oskar Mencer},
  title     = {Energy Reduction by Systematic Run-Time Reconfigurable Hardware Deactivation},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {4},
  pages     = {354--369},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-24568-8\_18},
  doi       = {10.1007/978-3-642-24568-8\_18},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/OsborneLCM11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/PlishkerSKB11,
  author    = {William Plishker and
               Nimish Sane and
               Mary Kiemb and
               Shuvra S. Bhattacharyya},
  title     = {Heterogeneous Design in Functional {DIF}},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {4},
  pages     = {391--408},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-24568-8\_20},
  doi       = {10.1007/978-3-642-24568-8\_20},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/PlishkerSKB11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/RullmannM11,
  author    = {Markus Rullmann and
               Renate Merker},
  title     = {A Cost Model for Partial Dynamic Reconfiguration},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {4},
  pages     = {370--390},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-24568-8\_19},
  doi       = {10.1007/978-3-642-24568-8\_19},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/RullmannM11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/SaidaniLFTB11,
  author    = {Tarik Saidani and
               Lionel Lacassagne and
               Joel Falcou and
               Claude Tadonki and
               Samir Bouaziz},
  title     = {Parallelization Schemes for Memory Optimization on the Cell Processor:
               {A} Case Study on the Harris Corner Detector},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {3},
  pages     = {177--200},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-19448-1\_10},
  doi       = {10.1007/978-3-642-19448-1\_10},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/SaidaniLFTB11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/SarkarT11,
  author    = {Subhradyuti Sarkar and
               Dean M. Tullsen},
  title     = {Data Layout for Cache Performance on a Multithreaded Architecture},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {3},
  pages     = {43--68},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-19448-1\_3},
  doi       = {10.1007/978-3-642-19448-1\_3},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/SarkarT11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/SazeidesMCK11,
  author    = {Yiannakis Sazeides and
               Andreas Moustakas and
               Kypros Constantinides and
               Marios Kleanthous},
  title     = {Improving Branch Prediction by Considering Affectors and Affectees
               Correlations},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {3},
  pages     = {69--88},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-19448-1\_4},
  doi       = {10.1007/978-3-642-19448-1\_4},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/SazeidesMCK11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/VandeputteE11,
  author    = {Frederik Vandeputte and
               Lieven Eeckhout},
  title     = {Characterizing Time-Varying Program Behavior Using Phase Complexity
               Surfaces},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {4},
  pages     = {21--41},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-24568-8\_2},
  doi       = {10.1007/978-3-642-24568-8\_2},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/VandeputteE11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/VandeputteE11a,
  author    = {Frederik Vandeputte and
               Lieven Eeckhout},
  title     = {Finding Extreme Behaviors in Microprocessor Workloads},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {4},
  pages     = {155--174},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-24568-8\_8},
  doi       = {10.1007/978-3-642-24568-8\_8},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/VandeputteE11a.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/WadaHMSNSKK11,
  author    = {Yasutaka Wada and
               Akihiro Hayashi and
               Takeshi Masuura and
               Jun Shirako and
               Hirofumi Nakano and
               Hiroaki Shikano and
               Keiji Kimura and
               Hironori Kasahara},
  title     = {A Parallelizing Compiler Cooperative Heterogeneous Multicore Processor
               Architecture},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {4},
  pages     = {215--233},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-24568-8\_11},
  doi       = {10.1007/978-3-642-24568-8\_11},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/WadaHMSNSKK11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/Waliullah11,
  author    = {M. M. Waliullah},
  title     = {Efficient Partial Roll-Backing Mechanism for Transactional Memory
               Systems},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {3},
  pages     = {256--274},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-19448-1\_14},
  doi       = {10.1007/978-3-642-19448-1\_14},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/Waliullah11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/WelcS11,
  author    = {Adam Welc and
               Bratin Saha},
  title     = {Software Transactional Memory Validation - Time and Space Considerations},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {4},
  pages     = {254--273},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-24568-8\_13},
  doi       = {10.1007/978-3-642-24568-8\_13},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/WelcS11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/WuYWHRGZ11,
  author    = {Nan Wu and
               Qianming Yang and
               Mei Wen and
               Yi He and
               Ju Ren and
               Maolin Guan and
               Chunyuan Zhang},
  title     = {Tiled Multi-Core Stream Architecture},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {4},
  pages     = {274--293},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-24568-8\_14},
  doi       = {10.1007/978-3-642-24568-8\_14},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/WuYWHRGZ11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/YuanYF11,
  author    = {Nan Yuan and
               Lei Yu and
               Dongrui Fan},
  title     = {An Efficient and Flexible Task Management for Many Cores},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {4},
  pages     = {294--310},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-24568-8\_15},
  doi       = {10.1007/978-3-642-24568-8\_15},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/YuanYF11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:journals/thipeac/2011-3,
  editor    = {Per Stenstr{\"{o}}m},
  title     = {Transactions on High-Performance Embedded Architectures and Compilers
               {III}},
  series    = {Lecture Notes in Computer Science},
  volume    = {6590},
  publisher = {Springer},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-19448-1},
  doi       = {10.1007/978-3-642-19448-1},
  isbn      = {978-3-642-19447-4},
  timestamp = {Tue, 14 May 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/2011-3.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:journals/thipeac/2011-4,
  editor    = {Per Stenstr{\"{o}}m},
  title     = {Transactions on High-Performance Embedded Architectures and Compilers
               {IV}},
  series    = {Lecture Notes in Computer Science},
  volume    = {6760},
  publisher = {Springer},
  year      = {2011},
  url       = {https://doi.org/10.1007/978-3-642-24568-8},
  doi       = {10.1007/978-3-642-24568-8},
  isbn      = {978-3-642-24567-1},
  timestamp = {Tue, 14 May 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/2011-4.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/Aggarwal09,
  author    = {Aneesh Aggarwal},
  title     = {Complexity Effective Bypass Networks},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {2},
  pages     = {201--221},
  year      = {2009},
  url       = {https://doi.org/10.1007/978-3-642-00904-4\_11},
  doi       = {10.1007/978-3-642-00904-4\_11},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/Aggarwal09.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/AhnP09,
  author    = {Minwook Ahn and
               Yunheung Paek},
  title     = {Fast Code Generation for Embedded Processors with Aliased Heterogeneous
               Registers},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {2},
  pages     = {149--172},
  year      = {2009},
  url       = {https://doi.org/10.1007/978-3-642-00904-4\_9},
  doi       = {10.1007/978-3-642-00904-4\_9},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/AhnP09.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/BhadauriaMST09,
  author    = {Major Bhadauria and
               Sally A. McKee and
               Karan Singh and
               Gary S. Tyson},
  title     = {Data Cache Techniques to Save Power and Deliver High Performance in
               Embedded Systems},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {2},
  pages     = {65--84},
  year      = {2009},
  url       = {https://doi.org/10.1007/978-3-642-00904-4\_5},
  doi       = {10.1007/978-3-642-00904-4\_5},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/BhadauriaMST09.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/CanedoAS09,
  author    = {Arquimedes Canedo and
               Ben A. Abderazek and
               Masahiro Sowa},
  title     = {Compiler Support for Code Size Reduction Using a Queue-Based Processor},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {2},
  pages     = {269--285},
  year      = {2009},
  url       = {https://doi.org/10.1007/978-3-642-00904-4\_14},
  doi       = {10.1007/978-3-642-00904-4\_14},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/CanedoAS09.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/ChanetCMNB09,
  author    = {Dominique Chanet and
               Javier Cabezas and
               Enric Morancho and
               Nacho Navarro and
               Koen De Bosschere},
  title     = {Linux Kernel Compaction through Cold Code Swapping},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {2},
  pages     = {173--200},
  year      = {2009},
  url       = {https://doi.org/10.1007/978-3-642-00904-4\_10},
  doi       = {10.1007/978-3-642-00904-4\_10},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/ChanetCMNB09.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/ChoiPD09,
  author    = {Woojin Choi and
               Seok{-}Jun Park and
               Michel Dubois},
  title     = {Accurate Instruction Pre-scheduling in Dynamically Scheduled Processors},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {2},
  pages     = {107--127},
  year      = {2009},
  url       = {https://doi.org/10.1007/978-3-642-00904-4\_7},
  doi       = {10.1007/978-3-642-00904-4\_7},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/ChoiPD09.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/GolanderW09,
  author    = {Amit Golander and
               Shlomo Weiss},
  title     = {Reexecution and Selective Reuse in Checkpoint Processors},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {2},
  pages     = {242--268},
  year      = {2009},
  url       = {https://doi.org/10.1007/978-3-642-00904-4\_13},
  doi       = {10.1007/978-3-642-00904-4\_13},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/GolanderW09.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/HuJK09,
  author    = {Chunling Hu and
               Daniel A. Jim{\'{e}}nez and
               Ulrich Kremer},
  title     = {Combining Edge Vector and Event Counter for Time-Dependent Power Behavior
               Characterization},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {2},
  pages     = {85--104},
  year      = {2009},
  url       = {https://doi.org/10.1007/978-3-642-00904-4\_6},
  doi       = {10.1007/978-3-642-00904-4\_6},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/HuJK09.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/IbrahimN09,
  author    = {Khaled Z. Ibrahim and
               Sma{\"{\i}}l Niar},
  title     = {Power-Aware Bus Coscheduling for Periodic Realtime Applications Running
               on Multiprocessor SoC},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {2},
  pages     = {286--306},
  year      = {2009},
  url       = {https://doi.org/10.1007/978-3-642-00904-4\_15},
  doi       = {10.1007/978-3-642-00904-4\_15},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/IbrahimN09.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/KeramidasXK09,
  author    = {Georgios Keramidas and
               Polychronis Xekalakis and
               Stefanos Kaxiras},
  title     = {Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {2},
  pages     = {4--22},
  year      = {2009},
  url       = {https://doi.org/10.1007/978-3-642-00904-4\_2},
  doi       = {10.1007/978-3-642-00904-4\_2},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/KeramidasXK09.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/KluyskensE09,
  author    = {Simon Kluyskens and
               Lieven Eeckhout},
  title     = {Branch Predictor Warmup for Sampled Simulation through Branch History
               Matching},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {2},
  pages     = {45--64},
  year      = {2009},
  url       = {https://doi.org/10.1007/978-3-642-00904-4\_4},
  doi       = {10.1007/978-3-642-00904-4\_4},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/KluyskensE09.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/MahoneySBP09,
  author    = {Patrick Mahoney and
               Yvon Savaria and
               Guy Bois and
               Patrice Plante},
  title     = {Performance Characterization for the Implementation of Content Addressable
               Memories Based on Parallel Hashing Memories},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {2},
  pages     = {307--325},
  year      = {2009},
  url       = {https://doi.org/10.1007/978-3-642-00904-4\_16},
  doi       = {10.1007/978-3-642-00904-4\_16},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/MahoneySBP09.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/NagarajanGK09,
  author    = {Vijay Nagarajan and
               Rajiv Gupta and
               Arvind Krishnaswamy},
  title     = {Compiler-Assisted Memory Encryption for Embedded Processors},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {2},
  pages     = {23--44},
  year      = {2009},
  url       = {https://doi.org/10.1007/978-3-642-00904-4\_3},
  doi       = {10.1007/978-3-642-00904-4\_3},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/NagarajanGK09.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/RochangeS09,
  author    = {Christine Rochange and
               Pascal Sainrat},
  title     = {A Context-Parameterized Model for Static Analysis of Execution Times},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {2},
  pages     = {222--241},
  year      = {2009},
  url       = {https://doi.org/10.1007/978-3-642-00904-4\_12},
  doi       = {10.1007/978-3-642-00904-4\_12},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/RochangeS09.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/StenstromW09,
  author    = {Per Stenstr{\"{o}}m and
               David B. Whalley},
  title     = {Introduction},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {2},
  pages     = {3},
  year      = {2009},
  url       = {https://doi.org/10.1007/978-3-642-00904-4\_1},
  doi       = {10.1007/978-3-642-00904-4\_1},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/StenstromW09.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/VandierendonckS09,
  author    = {Hans Vandierendonck and
               Andr{\'{e}} Seznec},
  title     = {Fetch Gating Control through Speculative Instruction Window Weighting},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {2},
  pages     = {128--148},
  year      = {2009},
  url       = {https://doi.org/10.1007/978-3-642-00904-4\_8},
  doi       = {10.1007/978-3-642-00904-4\_8},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/VandierendonckS09.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:journals/thipeac/2009-2,
  editor    = {Per Stenstr{\"{o}}m},
  title     = {Transactions on High-Performance Embedded Architectures and Compilers
               {II}},
  series    = {Lecture Notes in Computer Science},
  volume    = {5470},
  publisher = {Springer},
  year      = {2009},
  url       = {https://doi.org/10.1007/978-3-642-00904-4},
  doi       = {10.1007/978-3-642-00904-4},
  isbn      = {978-3-642-00903-7},
  timestamp = {Tue, 14 May 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/2009-2.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/BosschereLMNOPRSSST07,
  author    = {Koen De Bosschere and
               Wayne Luk and
               Xavier Martorell and
               Nacho Navarro and
               Michael F. P. O'Boyle and
               Dionisios N. Pnevmatikatos and
               Alex Ram{\'{\i}}rez and
               Pascal Sainrat and
               Andr{\'{e}} Seznec and
               Per Stenstr{\"{o}}m and
               Olivier Temam},
  title     = {High-Performance Embedded Architecture and Compilation Roadmap},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {1},
  pages     = {5--29},
  year      = {2007},
  url       = {https://doi.org/10.1007/978-3-540-71528-3\_2},
  doi       = {10.1007/978-3-540-71528-3\_2},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/BosschereLMNOPRSSST07.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/BuytaertVEB07,
  author    = {Dries Buytaert and
               Kris Venstermans and
               Lieven Eeckhout and
               Koen De Bosschere},
  title     = {{GCH:} Hints for Triggering Garbage Collections},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {1},
  pages     = {74--94},
  year      = {2007},
  url       = {https://doi.org/10.1007/978-3-540-71528-3\_6},
  doi       = {10.1007/978-3-540-71528-3\_6},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/BuytaertVEB07.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/ChenK07,
  author    = {Guilin Chen and
               Mahmut T. Kandemir},
  title     = {An Approach for Enhancing Inter-processor Data Locality on Chip Multiprocessors},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {1},
  pages     = {214--233},
  year      = {2007},
  url       = {https://doi.org/10.1007/978-3-540-71528-3\_14},
  doi       = {10.1007/978-3-540-71528-3\_14},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/ChenK07.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/DevosBCCDS07,
  author    = {Harald Devos and
               Kristof Beyls and
               Mark Christiaens and
               Jan M. Van Campenhout and
               Erik H. D'Hollander and
               Dirk Stroobandt},
  title     = {Finding and Applying Loop Transformations for Generating Optimized
               {FPGA} Implementations},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {1},
  pages     = {159--178},
  year      = {2007},
  url       = {https://doi.org/10.1007/978-3-540-71528-3\_11},
  doi       = {10.1007/978-3-540-71528-3\_11},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/DevosBCCDS07.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/FakhreddineAAJ07,
  author    = {Ghaffari Fakhreddine and
               Michel Auguin and
               Mohamed Abid and
               Maher Ben Jemaa},
  title     = {Dynamic and On-Line Design Space Exploration for Reconfigurable Architectures},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {1},
  pages     = {179--193},
  year      = {2007},
  url       = {https://doi.org/10.1007/978-3-540-71528-3\_12},
  doi       = {10.1007/978-3-540-71528-3\_12},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/FakhreddineAAJ07.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/FursinCOT07,
  author    = {Grigori Fursin and
               Albert Cohen and
               Michael F. P. O'Boyle and
               Olivier Temam},
  title     = {Quick and Practical Run-Time Evaluation of Multiple Program Optimizations},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {1},
  pages     = {34--53},
  year      = {2007},
  url       = {https://doi.org/10.1007/978-3-540-71528-3\_4},
  doi       = {10.1007/978-3-540-71528-3\_4},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/FursinCOT07.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/GeigerMT07,
  author    = {Michael J. Geiger and
               Sally A. McKee and
               Gary S. Tyson},
  title     = {Specializing Cache Structures for High Performance and Energy Conservation
               in Embedded Systems},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {1},
  pages     = {54--73},
  year      = {2007},
  url       = {https://doi.org/10.1007/978-3-540-71528-3\_5},
  doi       = {10.1007/978-3-540-71528-3\_5},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/GeigerMT07.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/KhatibBPBJBKHNJ07,
  author    = {Iyad Al Khatib and
               Davide Bertozzi and
               Francesco Poletti and
               Luca Benini and
               Axel Jantsch and
               Mohamed Bechara and
               Hasan Khalifeh and
               Mazen Hajjar and
               Rustam Nabiev and
               Sven Jonsson},
  title     = {Hardware/Software Architecture for Real-Time {ECG} Monitoring and
               Analysis Leveraging MPSoC Technology},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {1},
  pages     = {239--258},
  year      = {2007},
  url       = {https://doi.org/10.1007/978-3-540-71528-3\_16},
  doi       = {10.1007/978-3-540-71528-3\_16},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/KhatibBPBJBKHNJ07.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/McKee07,
  author    = {Sally A. McKee},
  title     = {Introduction to Part 3},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {1},
  pages     = {237--238},
  year      = {2007},
  url       = {https://doi.org/10.1007/978-3-540-71528-3\_15},
  doi       = {10.1007/978-3-540-71528-3\_15},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/McKee07.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/MolnosCHE07,
  author    = {Anca Mariana Molnos and
               Sorin Dan Cotofana and
               Marc J. M. Heijligers and
               Jos T. J. van Eijndhoven},
  title     = {Static Cache Partitioning Robustness Analysis for Embedded On-Chip
               Multi-processors},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {1},
  pages     = {279--297},
  year      = {2007},
  url       = {https://doi.org/10.1007/978-3-540-71528-3\_18},
  doi       = {10.1007/978-3-540-71528-3\_18},
  timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/MolnosCHE07.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/NethercoteBM07,
  author    = {Nicholas Nethercote and
               Doug Burger and
               Kathryn S. McKinley},
  title     = {Convergent Compilation Applied to Loop Unrolling},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {1},
  pages     = {140--158},
  year      = {2007},
  url       = {https://doi.org/10.1007/978-3-540-71528-3\_10},
  doi       = {10.1007/978-3-540-71528-3\_10},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/NethercoteBM07.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/NingK07,
  author    = {Ke Ning and
               David R. Kaeli},
  title     = {Power Aware External Bus Arbitration for System-on-a-Chip Embedded
               Systems},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {1},
  pages     = {116--135},
  year      = {2007},
  url       = {https://doi.org/10.1007/978-3-540-71528-3\_8},
  doi       = {10.1007/978-3-540-71528-3\_8},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/NingK07.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/OBoyleBC07,
  author    = {Michael F. P. O'Boyle and
               Fran{\c{c}}ois Bodin and
               Marcelo Cintra},
  title     = {Introduction to Part 2},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {1},
  pages     = {139},
  year      = {2007},
  url       = {https://doi.org/10.1007/978-3-540-71528-3\_9},
  doi       = {10.1007/978-3-540-71528-3\_9},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/OBoyleBC07.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/OliverFCA07,
  author    = {John Oliver and
               Diana Franklin and
               Frederic T. Chong and
               Venkatesh Akella},
  title     = {Using Application Bisection Bandwidth to Guide Tile Size Selection
               for the Synchroscalar Tile-Based Architecture},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {1},
  pages     = {259--278},
  year      = {2007},
  url       = {https://doi.org/10.1007/978-3-540-71528-3\_17},
  doi       = {10.1007/978-3-540-71528-3\_17},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/OliverFCA07.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/PinterW07,
  author    = {Shlomit S. Pinter and
               Israel Waldman},
  title     = {Selective Code Compression Scheme for Embedded Systems},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {1},
  pages     = {298--316},
  year      = {2007},
  url       = {https://doi.org/10.1007/978-3-540-71528-3\_19},
  doi       = {10.1007/978-3-540-71528-3\_19},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/PinterW07.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/RyooURKFH07,
  author    = {Shane Ryoo and
               Sain{-}Zee Ueng and
               Christopher I. Rodrigues and
               Robert E. Kidd and
               Matthew I. Frank and
               Wen{-}mei W. Hwu},
  title     = {Automatic Discovery of Coarse-Grained Parallelism in Media Applications},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {1},
  pages     = {194--213},
  year      = {2007},
  url       = {https://doi.org/10.1007/978-3-540-71528-3\_13},
  doi       = {10.1007/978-3-540-71528-3\_13},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/RyooURKFH07.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/ShiLL07,
  author    = {Weidong Shi and
               Chenghuai Lu and
               Hsien{-}Hsin S. Lee},
  title     = {Memory-Centric Security Architecture},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {1},
  pages     = {95--115},
  year      = {2007},
  url       = {https://doi.org/10.1007/978-3-540-71528-3\_7},
  doi       = {10.1007/978-3-540-71528-3\_7},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/ShiLL07.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/SonK07,
  author    = {Seung Woo Son and
               Mahmut T. Kandemir},
  title     = {A Prefetching Algorithm for Multi-speed Disks},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {1},
  pages     = {317--340},
  year      = {2007},
  url       = {https://doi.org/10.1007/978-3-540-71528-3\_20},
  doi       = {10.1007/978-3-540-71528-3\_20},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/SonK07.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/Stenstrom07,
  author    = {Per Stenstr{\"{o}}m},
  title     = {Introduction to Part 1},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {1},
  pages     = {33},
  year      = {2007},
  url       = {https://doi.org/10.1007/978-3-540-71528-3\_3},
  doi       = {10.1007/978-3-540-71528-3\_3},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/Stenstrom07.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/SusuMAAM07,
  author    = {Alex E. Susu and
               Michele Magno and
               Andrea Acquaviva and
               David Atienza and
               Giovanni De Micheli},
  title     = {Reconfiguration Strategies for Environmentally Powered Devices: Theoretical
               Analysis and Experimental Validation},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {1},
  pages     = {341--360},
  year      = {2007},
  url       = {https://doi.org/10.1007/978-3-540-71528-3\_21},
  doi       = {10.1007/978-3-540-71528-3\_21},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/SusuMAAM07.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/thipeac/Wilkes07,
  author    = {Maurice V. Wilkes},
  title     = {High Performance Processor Chips},
  journal   = {Trans. High Perform. Embed. Archit. Compil.},
  volume    = {1},
  pages     = {1--4},
  year      = {2007},
  url       = {https://doi.org/10.1007/978-3-540-71528-3\_1},
  doi       = {10.1007/978-3-540-71528-3\_1},
  timestamp = {Mon, 18 May 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/Wilkes07.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:journals/thipeac/2007-1,
  editor    = {Per Stenstr{\"{o}}m and
               Michael F. P. O'Boyle and
               Fran{\c{c}}ois Bodin and
               Marcelo Cintra and
               Sally A. McKee},
  title     = {Transactions on High-Performance Embedded Architectures and Compilers
               {I}},
  series    = {Lecture Notes in Computer Science},
  volume    = {4050},
  publisher = {Springer},
  year      = {2007},
  url       = {https://doi.org/10.1007/978-3-540-71528-3},
  doi       = {10.1007/978-3-540-71528-3},
  isbn      = {978-3-540-71527-6},
  timestamp = {Tue, 14 May 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/thipeac/2007-1.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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