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@article{DBLP:journals/ipsj/ChangJC09,
  author       = {Yao{-}Wen Chang and
                  Zhe{-}Wei Jiang and
                  Tung{-}Chieh Chen},
  title        = {Essential Issues in Analytical Placement Algorithms},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {2},
  pages        = {145--166},
  year         = {2009},
  url          = {https://doi.org/10.2197/ipsjtsldm.2.145},
  doi          = {10.2197/IPSJTSLDM.2.145},
  timestamp    = {Tue, 29 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ipsj/ChangJC09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/DongN09,
  author       = {Qing Dong and
                  Shigetoshi Nakatake},
  title        = {Structured Placement with Topological Regularity Evaluation},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {2},
  pages        = {222--238},
  year         = {2009},
  url          = {https://doi.org/10.2197/ipsjtsldm.2.222},
  doi          = {10.2197/IPSJTSLDM.2.222},
  timestamp    = {Tue, 29 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ipsj/DongN09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/Fujita09,
  author       = {Masahiro Fujita},
  title        = {Trends in Formal Verification Techniques for C-based Hardware Designs},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {2},
  pages        = {2--17},
  year         = {2009},
  url          = {https://doi.org/10.2197/ipsjtsldm.2.2},
  doi          = {10.2197/IPSJTSLDM.2.2},
  timestamp    = {Tue, 29 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ipsj/Fujita09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/GeCY09,
  author       = {Liangwei Ge and
                  Song Chen and
                  Takeshi Yoshimura},
  title        = {Exploration of Schedule Space by Random Walk},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {2},
  pages        = {30--42},
  year         = {2009},
  url          = {https://doi.org/10.2197/ipsjtsldm.2.30},
  doi          = {10.2197/IPSJTSLDM.2.30},
  timestamp    = {Tue, 29 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ipsj/GeCY09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/HamadaSKSYMN09,
  author       = {Naohiro Hamada and
                  Yuki Shiga and
                  Takao Konishi and
                  Hiroshi Saito and
                  Tomohiro Yoneda and
                  Chris J. Myers and
                  Takashi Nanya},
  title        = {A Behavioral Synthesis System for Asynchronous Circuits with Bundled-data
                  Implementation},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {2},
  pages        = {64--79},
  year         = {2009},
  url          = {https://doi.org/10.2197/ipsjtsldm.2.64},
  doi          = {10.2197/IPSJTSLDM.2.64},
  timestamp    = {Tue, 29 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ipsj/HamadaSKSYMN09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/HigamiSTKT09,
  author       = {Yoshinobu Higami and
                  Kewal K. Saluja and
                  Hiroshi Takahashi and
                  Shin{-}ya Kobayashi and
                  Yuzo Takamatsu},
  title        = {An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {2},
  pages        = {250--262},
  year         = {2009},
  url          = {https://doi.org/10.2197/ipsjtsldm.2.250},
  doi          = {10.2197/IPSJTSLDM.2.250},
  timestamp    = {Tue, 29 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ipsj/HigamiSTKT09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/HiromotoON09,
  author       = {Masayuki Hiromoto and
                  Hiroyuki Ochi and
                  Yukihiro Nakamura},
  title        = {An Asynchronous IEEE-754-standard Single-precision Floating-point
                  Divider for {FPGA}},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {2},
  pages        = {103--113},
  year         = {2009},
  url          = {https://doi.org/10.2197/ipsjtsldm.2.103},
  doi          = {10.2197/IPSJTSLDM.2.103},
  timestamp    = {Tue, 29 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ipsj/HiromotoON09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/HuangLI09,
  author       = {Yiqing Huang and
                  Qin Liu and
                  Takeshi Ikenaga},
  title        = {Macroblock Feature Based Adaptive Propagate Partial {SAD} Architecture
                  for {HDTV} Application},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {2},
  pages        = {263--273},
  year         = {2009},
  url          = {https://doi.org/10.2197/ipsjtsldm.2.263},
  doi          = {10.2197/IPSJTSLDM.2.263},
  timestamp    = {Mon, 23 Nov 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/ipsj/HuangLI09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/InagakiSNMI09,
  author       = {Ryosuke Inagaki and
                  Norio Sadachika and
                  Dondee Navarro and
                  Mitiko Miura{-}Mattausch and
                  Yasuaki Inoue},
  title        = {A GIDL-Current Model for Advanced {MOSFET} Technologies without Binning},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {2},
  pages        = {93--102},
  year         = {2009},
  url          = {https://doi.org/10.2197/ipsjtsldm.2.93},
  doi          = {10.2197/IPSJTSLDM.2.93},
  timestamp    = {Tue, 29 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ipsj/InagakiSNMI09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/ItoS09,
  author       = {Kazuhito Ito and
                  Hidekazu Seto},
  title        = {Reducing Power Dissipation of Data Communications on {LSI} with Scheduling
                  Exploration},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {2},
  pages        = {53--63},
  year         = {2009},
  url          = {https://doi.org/10.2197/ipsjtsldm.2.53},
  doi          = {10.2197/IPSJTSLDM.2.53},
  timestamp    = {Tue, 29 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ipsj/ItoS09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/JiLIG09,
  author       = {Wen Ji and
                  Xing Li and
                  Takeshi Ikenaga and
                  Satoshi Goto},
  title        = {A High Throughput {LDPC} Decoder Design Based on Novel Delta-value
                  Message-passing Schedule},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {2},
  pages        = {122--130},
  year         = {2009},
  url          = {https://doi.org/10.2197/ipsjtsldm.2.122},
  doi          = {10.2197/IPSJTSLDM.2.122},
  timestamp    = {Tue, 29 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ipsj/JiLIG09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/KodamaM09,
  author       = {Sho Kodama and
                  Yusuke Matsunaga},
  title        = {Binding Refinement for Multiplexer Reduction},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {2},
  pages        = {43--52},
  year         = {2009},
  url          = {https://doi.org/10.2197/ipsjtsldm.2.43},
  doi          = {10.2197/IPSJTSLDM.2.43},
  timestamp    = {Tue, 29 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ipsj/KodamaM09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/KunduLG09,
  author       = {Sudipta Kundu and
                  Sorin Lerner and
                  Rajesh Gupta},
  title        = {High-Level Verification},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {2},
  pages        = {131--144},
  year         = {2009},
  url          = {https://doi.org/10.2197/ipsjtsldm.2.131},
  doi          = {10.2197/IPSJTSLDM.2.131},
  timestamp    = {Tue, 29 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ipsj/KunduLG09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/MatsumuraIY09,
  author       = {Tadayuki Matsumura and
                  Tohru Ishihara and
                  Hiroto Yasuura},
  title        = {An Optimization Technique for Low-Energy Embedded Memory Systems},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {2},
  pages        = {239--249},
  year         = {2009},
  url          = {https://doi.org/10.2197/ipsjtsldm.2.239},
  doi          = {10.2197/IPSJTSLDM.2.239},
  timestamp    = {Mon, 26 Oct 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/ipsj/MatsumuraIY09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/MatsunagaKM09,
  author       = {Taeko Matsunaga and
                  Shinji Kimura and
                  Yusuke Matsunaga},
  title        = {Framework for Parallel Prefix Adder Synthesis Considering Switching
                  Activities},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {2},
  pages        = {212--221},
  year         = {2009},
  url          = {https://doi.org/10.2197/ipsjtsldm.2.212},
  doi          = {10.2197/IPSJTSLDM.2.212},
  timestamp    = {Tue, 29 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ipsj/MatsunagaKM09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/Onodera09,
  author       = {Hidetoshi Onodera},
  title        = {Message from the Editor-in-Chief},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {2},
  pages        = {1},
  year         = {2009},
  url          = {https://doi.org/10.2197/ipsjtsldm.2.1},
  doi          = {10.2197/IPSJTSLDM.2.1},
  timestamp    = {Tue, 29 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ipsj/Onodera09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/TakamiyaS09,
  author       = {Makoto Takamiya and
                  Takayasu Sakurai},
  title        = {Low Power {VLSI} Circuit Design with Fine-Grain Voltage Engineering},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {2},
  pages        = {18--29},
  year         = {2009},
  url          = {https://doi.org/10.2197/ipsjtsldm.2.18},
  doi          = {10.2197/IPSJTSLDM.2.18},
  timestamp    = {Tue, 29 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ipsj/TakamiyaS09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/TakaseTT09,
  author       = {Hideki Takase and
                  Hiroyuki Tomiyama and
                  Hiroaki Takada},
  title        = {Partitioning and Allocation of Scratch-Pad Memory in Priority-Based
                  Multi-Task Systems},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {2},
  pages        = {180--188},
  year         = {2009},
  url          = {https://doi.org/10.2197/ipsjtsldm.2.180},
  doi          = {10.2197/IPSJTSLDM.2.180},
  timestamp    = {Tue, 29 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ipsj/TakaseTT09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/TakataM09,
  author       = {Taiga Takata and
                  Yusuke Matsunaga},
  title        = {Area Recovery under Depth Constraint for Technology Mapping for LUT-based
                  FPGAs},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {2},
  pages        = {200--211},
  year         = {2009},
  url          = {https://doi.org/10.2197/ipsjtsldm.2.200},
  doi          = {10.2197/IPSJTSLDM.2.200},
  timestamp    = {Tue, 29 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ipsj/TakataM09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/TakeuchiHK09,
  author       = {Sho Takeuchi and
                  Kiyoharu Hamaguchi and
                  Toshinobu Kashiwabara},
  title        = {Checker Generation of Assertions with Local Variables for Model Checking},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {2},
  pages        = {80--92},
  year         = {2009},
  url          = {https://doi.org/10.2197/ipsjtsldm.2.80},
  doi          = {10.2197/IPSJTSLDM.2.80},
  timestamp    = {Tue, 29 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ipsj/TakeuchiHK09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/WeiIG09,
  author       = {Xianghui Wei and
                  Takeshi Ikenaga and
                  Satoshi Goto},
  title        = {A Low Bandwidth Integer Motion Estimation Module for {MPEG-2} to {H.264}
                  Transcoding},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {2},
  pages        = {114--121},
  year         = {2009},
  url          = {https://doi.org/10.2197/ipsjtsldm.2.114},
  doi          = {10.2197/IPSJTSLDM.2.114},
  timestamp    = {Tue, 29 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ipsj/WeiIG09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/YamaguchiIIY09,
  author       = {Seiichiro Yamaguchi and
                  Yuriko Ishitobi and
                  Tohru Ishihara and
                  Hiroto Yasuura},
  title        = {Single-Cycle-Accessible Two-Level Caches and Compilation Technique
                  for Energy Reducion},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {2},
  pages        = {189--199},
  year         = {2009},
  url          = {https://doi.org/10.2197/ipsjtsldm.2.189},
  doi          = {10.2197/IPSJTSLDM.2.189},
  timestamp    = {Mon, 26 Oct 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/ipsj/YamaguchiIIY09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/ZengTT09,
  author       = {Gang Zeng and
                  Hiroyuki Tomiyama and
                  Hiroaki Takada},
  title        = {A Generalized Framework for Energy Savings in Hard Real-Time Embedded
                  Systems},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {2},
  pages        = {167--179},
  year         = {2009},
  url          = {https://doi.org/10.2197/ipsjtsldm.2.167},
  doi          = {10.2197/IPSJTSLDM.2.167},
  timestamp    = {Tue, 29 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ipsj/ZengTT09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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