Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDSearch dblp for Publications
export results for "toc:db/conf/fpga/fpga2019.bht:"
download as .bib file
@inproceedings{DBLP:conf/fpga/AsiaticiI19,
author = {Mikhail Asiatici and
Paolo Ienne},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands
of Outstanding Misses in FPGAs},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {310--319},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293901},
doi = {10.1145/3289602.3293901},
timestamp = {Tue, 05 Mar 2019 07:04:43 +0100},
biburl = {https://dblp.org/rec/conf/fpga/AsiaticiI19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/AzariDV19,
author = {Elham Azari and
Aykut Dengi and
Sarma B. K. Vrudhula},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {An Energy-Efficient {FPGA} Implementation of an {LSTM} Network Using
Approximate Computing},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {305--306},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293989},
doi = {10.1145/3289602.3293989},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/AzariDV19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/BandaraEKK19,
author = {Sahan Bandara and
Alan Ehret and
Donato Kava and
Michel A. Kinsy},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {{BRISC-V:} An Open-Source Architecture Design Space Exploration Toolbox},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {306},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293991},
doi = {10.1145/3289602.3293991},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/BandaraEKK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/BestaFBLH19,
author = {Maciej Besta and
Marc Fischer and
Tal Ben{-}Nun and
Johannes de Fine Licht and
Torsten Hoefler},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Substream-Centric Maximum Matchings on {FPGA}},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {152--161},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293916},
doi = {10.1145/3289602.3293916},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/BestaFBLH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/BiancolinKKKWBA19,
author = {David Biancolin and
Sagar Karandikar and
Donggyu Kim and
Jack Koenig and
Andrew Waterman and
Jonathan Bachrach and
Krste Asanovic},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {{FASED:} FPGA-Accelerated Simulation and Evaluation of {DRAM}},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {330--339},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293894},
doi = {10.1145/3289602.3293894},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/BiancolinKKKWBA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/BoutrosEYB19,
author = {Andrew Boutros and
Mohamed Eldafrawy and
Sadegh Yazdanshenas and
Vaughn Betz},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Math Doesn't Have to be Hard: Logic Block Architectures to Enhance
Low-Precision Multiply-Accumulate on FPGAs},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {94--103},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293912},
doi = {10.1145/3289602.3293912},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/BoutrosEYB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/CaoZYXNZLWZ19,
author = {Shijie Cao and
Chen Zhang and
Zhuliang Yao and
Wencong Xiao and
Lanshun Nie and
De{-}chen Zhan and
Yunxin Liu and
Ming Wu and
Lintao Zhang},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Efficient and Effective Sparse {LSTM} on {FPGA} with Bank-Balanced
Sparsity},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {63--72},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293898},
doi = {10.1145/3289602.3293898},
timestamp = {Sat, 15 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/CaoZYXNZLWZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ChangZL19,
author = {Chia{-}Wei Chang and
Zi{-}Qi Zhong and
Jing{-}Jia Liou},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {A {FPGA} Implementation of Farneback Optical Flow by High-Level Synthesis},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {309},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3294005},
doi = {10.1145/3289602.3294005},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/ChangZL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/Chen19,
author = {Deming Chen},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {FPGAs in Supercomputers: Opportunity or Folly?},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {201},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293929},
doi = {10.1145/3289602.3293929},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/Chen19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ChenBC19,
author = {Zhe Chen and
Hugh T. Blair and
Jason Cong},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {{LANMC:} LSTM-Assisted Non-Rigid Motion Correction on {FPGA} for Calcium
Image Stabilization},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {104--109},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293919},
doi = {10.1145/3289602.3293919},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/ChenBC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ChenHZHC19,
author = {Yao Chen and
Jiong He and
Xiaofan Zhang and
Cong Hao and
Deming Chen},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Cloud-DNN: An Open Framework for Mapping {DNN} Models to Cloud FPGAs},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {73--82},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293915},
doi = {10.1145/3289602.3293915},
timestamp = {Tue, 19 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/ChenHZHC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ChenS19,
author = {Hongzheng Chen and
Minghua Shen},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {A Deep-Reinforcement-Learning-Based Scheduler for High-Level Synthesis},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {117},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293934},
doi = {10.1145/3289602.3293934},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/ChenS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ChenXYLC19,
author = {Chen Chen and
Jun Xia and
Wenmin Yang and
Kang Li and
Zhilei Chai},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {A PYNQ-compliant Online Platform for Zynq-based {DNN} Developers},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {185},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293961},
doi = {10.1145/3289602.3293961},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/ChenXYLC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ChengFCAC19,
author = {Jianyi Cheng and
Shane T. Fleming and
Yu Ting Chen and
Jason Helge Anderson and
George A. Constantinides},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {{EASY:} Efficient Arbiter SYnthesis from Multi-threaded Code},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {142--151},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293899},
doi = {10.1145/3289602.3293899},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/ChengFCAC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ChiCCW19,
author = {Yuze Chi and
Young{-}kyu Choi and
Jason Cong and
Jie Wang},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Rapid Cycle-Accurate Simulator for High-Level Synthesis},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {178--183},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293918},
doi = {10.1145/3289602.3293918},
timestamp = {Wed, 05 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/ChiCCW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/CoughlinCWKW19,
author = {Aimee Coughlin and
Greg Cusack and
Jack Wampler and
Eric Keller and
Eric Wustrow},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Breaking the Trust Dependence on Third Party Processes for Reconfigurable
Secure Hardware},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {282--291},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293895},
doi = {10.1145/3289602.3293895},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/CoughlinCWKW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/DaravKVK19,
author = {Nima Karimpour Darav and
Andrew A. Kennings and
Kristofer Vorwerk and
Arun Kundu},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Multi-Commodity Flow-Based Spreading in a Commercial Analytic Placer},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {122--131},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293896},
doi = {10.1145/3289602.3293896},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/DaravKVK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/DassNMS19,
author = {Jyotikrishna Dass and
Yashwardhan Narawane and
Rabi N. Mahapatra and
Vivek Sarin},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {FPGA-based Distributed Edge Training of {SVM}},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {121},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293954},
doi = {10.1145/3289602.3293954},
timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/DassNMS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/DiaoJLY0DDSXZL19,
author = {Lansong Diao and
Zhao Jiang and
Hao Liang and
Chang'an Ye and
Kai Chen and
Li Ding and
Shunli Dou and
Meng Sun and
Lixue Xia and
Jiansong Zhang and
Wei Lin},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {{PAI-FCNN:} {FPGA} Based {CNN} Inference System},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {184},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293957},
doi = {10.1145/3289602.3293957},
timestamp = {Mon, 12 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/DiaoJLY0DDSXZL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/DingWLXW019,
author = {Caiwen Ding and
Shuo Wang and
Ning Liu and
Kaidi Xu and
Yanzhi Wang and
Yun Liang},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {{REQ-YOLO:} {A} Resource-Aware, Efficient Quantization Framework for
Object Detection on FPGAs},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {33--42},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293904},
doi = {10.1145/3289602.3293904},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/DingWLXW019.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/DuarteHHJKKLNPR19,
author = {Javier M. Duarte and
Song Han and
Philip C. Harris and
Sergo Jindariani and
Edward Kreinar and
Benjamin Kreis and
Vladimir Loncar and
Jennifer Ngadiuba and
Maurizio Pierini and
Dylan S. Rankin and
Ryan A. Rivera and
Sioni Summers and
Nhan Tran and
Zhenbin Wu},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Fast Inference of Deep Neural Networks for Real-time Particle Physics
Applications},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {305},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293986},
doi = {10.1145/3289602.3293986},
timestamp = {Thu, 28 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/DuarteHHJKKLNPR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/DuttaYMMR19,
author = {Sandeep Dutta and
Adnan Yunus and
Artem Marisov and
Matt Menezes and
Somayeh Rahimipour},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Visual System Integrator: Invited Tutorial},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {10--13},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293926},
doi = {10.1145/3289602.3293926},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/DuttaYMMR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/EscobedoL19,
author = {Juan Escobedo and
Mingjie Lin},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Optimizing Order-Associative Kernel Computation with Joint Memory
Banking and Data Reuse},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {189--190},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293980},
doi = {10.1145/3289602.3293980},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/EscobedoL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/EskandariTLC19,
author = {Nariman Eskandari and
Naif Tarafdar and
Daniel Ly{-}Ma and
Paul Chow},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {A Modular Heterogeneous Stack for Deploying FPGAs and CPUs in the
Data Center},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {262--271},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293909},
doi = {10.1145/3289602.3293909},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/EskandariTLC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/FengZLSZ19,
author = {Liang Feng and
Jieru Zhao and
Tingyuan Liang and
Sharad Sinha and
Wei Zhang},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {A Hybrid Data-Consistent Framework for Link-Aware AccessManagement
in Emerging {CPU-FPGA} Platforms},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {188},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293973},
doi = {10.1145/3289602.3293973},
timestamp = {Tue, 05 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/FengZLSZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/FuZSLZ19,
author = {Cheng Fu and
Shilin Zhu and
Hao Su and
Ching{-}En Lee and
Jishen Zhao},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Towards Fast and Energy-Efficient Binarized Neural Network Inference
on {FPGA}},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {306},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293990},
doi = {10.1145/3289602.3293990},
timestamp = {Wed, 11 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/FuZSLZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/GaideGRB19,
author = {Brian Gaide and
Dinesh Gaitonde and
Chirag Ravishankar and
Trevor Bauer},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Xilinx Adaptive Compute Acceleration Platform: Versal\({}^{\mbox{TM}}\)
Architecture},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {84--93},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293906},
doi = {10.1145/3289602.3293906},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/GaideGRB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/GaoR19,
author = {Tianqi Gao and
Rob A. Rutenbar},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {A Pixel-Parallel Virtual-Image Architecture for High Performance and
Power Efficient Graph Cuts Inference},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {120},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293948},
doi = {10.1145/3289602.3293948},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/GaoR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/GargWPK19,
author = {Tushar Garg and
Saud Wasly and
Rodolfo Pellizzoni and
Nachiket Kapre},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {HopliteBuf: {FPGA} NoCs with Provably Stall-Free FIFOs},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {222--231},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293917},
doi = {10.1145/3289602.3293917},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/GargWPK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/GlickGNW19,
author = {Dallon Glick and
Jesse Grigg and
Brent E. Nelson and
Michael J. Wirthlin},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Maverick: {A} Stand-alone {CAD} Flow for Xilinx 7-Series FPGAs},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {306--307},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293997},
doi = {10.1145/3289602.3293997},
timestamp = {Wed, 06 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/GlickGNW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/GuYSPFXW19,
author = {Yanjie Gu and
Jian Yu and
Tieli Sun and
Chen Pan and
Zhenhao Feng and
Liewei Xu and
Chang Wu},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Highly Efficient Sparse Neural Network Computing: Hardware and Software
Solutions},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {121},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293952},
doi = {10.1145/3289602.3293952},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/GuYSPFXW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/GuoLYNLWY19,
author = {Kaiyuan Guo and
Shuang Liang and
Jincheng Yu and
Xuefei Ning and
Wenshuo Li and
Yu Wang and
Huazhong Yang},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Compressed {CNN} Training with FPGA-based Accelerator},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {189},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293977},
doi = {10.1145/3289602.3293977},
timestamp = {Wed, 21 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/GuoLYNLWY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/HardieckKMZ19,
author = {Martin Hardieck and
Martin Kumm and
Konrad M{\"{o}}ller and
Peter Zipf},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Reconfigurable Convolutional Kernels for Neural Networks on FPGAs},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {43--52},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293905},
doi = {10.1145/3289602.3293905},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/HardieckKMZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/HeKZ19,
author = {Xin He and
Liu Ke and
Xuan Zhang},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {SparseBNN: Joint Algorithm/Hardware Optimization to Exploit Structured
Sparsity in Binary Neural Network},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {117--118},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293937},
doi = {10.1145/3289602.3293937},
timestamp = {Thu, 02 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/HeKZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/HeZYLL19,
author = {Anping He and
Jinlin Zhang and
Lvying Yu and
Pengfei Li and
Lian Li},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {How to Accelerate {FPGA} Application in an Asynchronous Way?},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {304},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293953},
doi = {10.1145/3289602.3293953},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/HeZYLL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/IbanezBMZ19,
author = {Stephen Ibanez and
Gordon J. Brebner and
Nick McKeown and
Noa Zilberman},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {The P4-{\textgreater}NetFPGA Workflow for Line-Rate Packet Processing},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {1--9},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293924},
doi = {10.1145/3289602.3293924},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/IbanezBMZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/JiangZSZYSH19,
author = {Weiwen Jiang and
Xinyi Zhang and
Edwin Hsing{-}Mean Sha and
Qingfeng Zhuge and
Lei Yang and
Yiyu Shi and
Jingtong Hu},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {{XFER:} {A} Novel Design to Achieve Super-Linear Performance on Multiple
FPGAs for Real-Time {AI}},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {305},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293988},
doi = {10.1145/3289602.3293988},
timestamp = {Tue, 13 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/JiangZSZYSH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/JinF19,
author = {Zheming Jin and
Hal Finkel},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Base64 Encoding on OpenCL {FPGA} Platform},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {116},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293932},
doi = {10.1145/3289602.3293932},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/JinF19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/JinF19a,
author = {Zheming Jin and
Hal Finkel},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Nuclear Reactor Simulations on OpenCL {FPGA} Platform},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {304},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293983},
doi = {10.1145/3289602.3293983},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/JinF19a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/JingLY19,
author = {Lu Jing and
Jun Liu and
FuHai Yu},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {A Deep Learning Inference Accelerator Based on Model Compression on
{FPGA}},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {118},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293938},
doi = {10.1145/3289602.3293938},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/JingLY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/JohnsenS19,
author = {Carl{-}Johannes Johnsen and
Kenneth Skovhede},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Building {FPGA} State Machines from Sequential Code},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {186},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293965},
doi = {10.1145/3289602.3293965},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/JohnsenS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/JosipovicGI19,
author = {Lana Josipovic and
Andrea Guerrieri and
Paolo Ienne},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Speculative Dataflow Circuits},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {162--171},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293914},
doi = {10.1145/3289602.3293914},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/JosipovicGI19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/KapralosC19,
author = {Michael P. Kapralos and
John A. Chandy},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {HOTMeTaL: Hardware Optimization Tool for Memory Table and Logic Conversion},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {307--308},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3294000},
doi = {10.1145/3289602.3294000},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/KapralosC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/KellerW19,
author = {Andrew M. Keller and
Michael J. Wirthlin},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Impact of Soft Errors on Large-Scale {FPGA} Cloud Computing},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {272--281},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293911},
doi = {10.1145/3289602.3293911},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/KellerW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/KoehnA19,
author = {Thaddeus Koehn and
Peter Athanas},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Scheduling Data in Neural Network Applications},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {116},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293930},
doi = {10.1145/3289602.3293930},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/KoehnA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/Konda19,
author = {Venkat Konda},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Hierarchical {FPGA} Fabrics using 2D-Benes-BFT-Pyramid Network Layouts
with Optimizations},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {307},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293998},
doi = {10.1145/3289602.3293998},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/Konda19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/Konda19a,
author = {Venkat Konda},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Flat {FPGA} Fabrics Derived from 2D-Benes-BFT-Pyramid Networks with
Optimizations and Enhancements},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {307},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293999},
doi = {10.1145/3289602.3293999},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/Konda19a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/KorolijaS19,
author = {Dario Korolija and
Mirjana Stojilovic},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Design and Implementation of a Deterministic {FPGA} Router on a {CPU+FPGA}
Acceleration Platform},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {186},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293966},
doi = {10.1145/3289602.3293966},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/KorolijaS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/KucherenkoNI19,
author = {Anastasiia Kucherenko and
Stefan Nikolic and
Paolo Ienne},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {On Feasibility of FPGAs Without Dedicated Programmable Interconnect
Structure},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {188},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293974},
doi = {10.1145/3289602.3293974},
timestamp = {Wed, 07 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/KucherenkoNI19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LaiCHWYZCZ19,
author = {Yi{-}Hsiang Lai and
Yuze Chi and
Yuwei Hu and
Jie Wang and
Cody Hao Yu and
Yuan Zhou and
Jason Cong and
Zhiru Zhang},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {HeteroCL: {A} Multi-Paradigm Programming Infrastructure for Software-Defined
Reconfigurable Computing},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {242--251},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293910},
doi = {10.1145/3289602.3293910},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/LaiCHWYZCZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LanGZXNLC19,
author = {Yazhu Lan and
Qingli Guo and
Guohe Zhang and
Yuanchao Xu and
Kent W. Nixon and
Hai Helen Li and
Yiran Chen},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Fast Confidence Detection: One Hot Way to Detect Adversarial Attacks
via Sensor Pattern Noise Fingerprinting},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {188--189},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293975},
doi = {10.1145/3289602.3293975},
timestamp = {Mon, 04 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/LanGZXNLC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LanghammerBG19,
author = {Martin Langhammer and
Gregg Baeckler and
Sergey Gribok},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Fractal Synthesis: Invited Tutorial},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {202--211},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293927},
doi = {10.1145/3289602.3293927},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/LanghammerBG19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LavinK19,
author = {Chris Lavin and
Alireza Kaviani},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Build Your Own Domain-specific Solutions with RapidWright: Invited
Tutorial},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {14--22},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293928},
doi = {10.1145/3289602.3293928},
timestamp = {Thu, 17 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/LavinK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LiDYP19,
author = {Wuxi Li and
Mehrdad E. Dehkordi and
Stephen Yang and
David Z. Pan},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Simultaneous Placement and Clock Tree Construction for Modern FPGAs},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {132--141},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293897},
doi = {10.1145/3289602.3293897},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/LiDYP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LiXZPWL19,
author = {Zhengjie Li and
Yuanlong Xiao and
Yufan Zhang and
Yunbing Pang and
Jian Wang and
Jinmei Lai},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Transistor-Level Optimization Methodology for {GRM} {FPGA} Interconnect
Circuits},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {121},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293955},
doi = {10.1145/3289602.3293955},
timestamp = {Thu, 17 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/LiXZPWL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LimBW19,
author = {Katie Lim and
Jonathan Balkind and
David Wentzlaff},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {JuxtaPiton: Enabling Heterogeneous-ISA Research with {RISC-V} and
{SPARC} {FPGA} Soft-cores},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {184},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293958},
doi = {10.1145/3289602.3293958},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/LimBW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/LiuC19,
author = {Jie Liu and
Jason Cong},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Dataflow Systolic Array Implementations of Matrix Decomposition Using
High Level Synthesis},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {187},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293969},
doi = {10.1145/3289602.3293969},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/LiuC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/Lu0HLCZ19,
author = {Liqiang Lu and
Yun Liang and
Ruirui Huang and
Wei Lin and
Xiaoyuan Cui and
Jiansong Zhang},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Speedy: An Accelerator for Sparse Convolutional Neural Networks on
FPGAs},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {187},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293970},
doi = {10.1145/3289602.3293970},
timestamp = {Mon, 12 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/Lu0HLCZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/MalikK19,
author = {Gurshaant Singh Malik and
Nachiket Kapre},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Enhancing Butterfly Fat Tree NoCs for FPGAs with Lightweight Flow
Control},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {308},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3294002},
doi = {10.1145/3289602.3294002},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/MalikK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/MannosDS19,
author = {Tom J. Mannos and
Brian Dziki and
Moslema Sharif},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Fault Testing a Synthesizable Embedded Processor at Gate Level using
UltraScale {FPGA} Emulation},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {116},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293931},
doi = {10.1145/3289602.3293931},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/MannosDS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/MaragosLSP19,
author = {Konstantinos Maragos and
George Lentaris and
Dimitrios Soudris and
Vasilis F. Pavlidis},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {PVT-Aware Sensing and Voltage Scaling for Energy Efficient FPGAs},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {190},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293981},
doi = {10.1145/3289602.3293981},
timestamp = {Wed, 31 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/MaragosLSP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/NakaharaJSS19,
author = {Hiroki Nakahara and
Akira Jinguji and
Masayuki Shimoda and
Shimpei Sato},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {An FPGA-based Fine Tuning Accelerator for a Sparse {CNN}},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {186},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293967},
doi = {10.1145/3289602.3293967},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/NakaharaJSS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/NoronhaZGLW19,
author = {Daniel Holanda Noronha and
Ruizhe Zhao and
Jeffrey Goeders and
Wayne Luk and
Steven J. E. Wilton},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {On-chip {FPGA} Debug Instrumentation for Machine Learning Applications},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {110--115},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293922},
doi = {10.1145/3289602.3293922},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/NoronhaZGLW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/NurvitadhiKJBST19,
author = {Eriko Nurvitadhi and
Dongup Kwon and
Ali Jafari and
Andrew Boutros and
Jaewoong Sim and
Phillip Tomson and
Huseyin Sumbul and
Gregory K. Chen and
Phil C. Knag and
Raghavan Kumar and
Ram Krishnamurthy and
Debbie Marr and
Sergey Gribok and
Bogdan Pasca and
Martin Langhammer and
Aravind Dasu},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Evaluating and Enhancing Intel{\textregistered} Stratix{\textregistered}
10 FPGAs for Persistent Real-Time {AI}},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {119},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293943},
doi = {10.1145/3289602.3293943},
timestamp = {Sun, 03 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/NurvitadhiKJBST19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ProvelengiosRPE19,
author = {George Provelengios and
Chethan Ramesh and
Shivukumar B. Patil and
Ken Eguro and
Russell Tessier and
Daniel E. Holcomb},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Characterization of Long Wire Data Leakage in Deep Submicron FPGAs},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {292--297},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293923},
doi = {10.1145/3289602.3293923},
timestamp = {Fri, 07 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/ProvelengiosRPE19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/RampalliSBTK19,
author = {Sahithi Rampalli and
Natasha Sehgal and
Ishita Bindlish and
Tanya Tyagi and
Pawan Kumar},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Efficient {FPGA} Implementation of Conjugate Gradient Methods for
Laplacian System using {HLS}},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {308--309},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3294004},
doi = {10.1145/3289602.3294004},
timestamp = {Tue, 28 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/RampalliSBTK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/RozhkoC19,
author = {Daniel Rozhko and
Paul Chow},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {The Network Management Unit {(NMU):} Securing Network Access for Direct-Connected
FPGAs},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {232--241},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293903},
doi = {10.1145/3289602.3293903},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/RozhkoC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/SalamatIKR19,
author = {Sahand Salamat and
Mohsen Imani and
Behnam Khaleghi and
Tajana Rosing},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {{F5-HD:} Fast Flexible FPGA-based Framework for Refreshing Hyperdimensional
Computing},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {53--62},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293913},
doi = {10.1145/3289602.3293913},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/SalamatIKR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ShaoLHL019,
author = {Zhiyuan Shao and
Ruoshi Li and
Diqing Hu and
Xiaofei Liao and
Hai Jin},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Improving Performance of Graph Processing on {FPGA-DRAM} Platform
by Two-level Vertex Caching},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {320--329},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293900},
doi = {10.1145/3289602.3293900},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/ShaoLHL019.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ShenWHWZ19,
author = {Junzhong Shen and
Deguang Wang and
You Huang and
Mei Wen and
Chunyuan Zhang},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Accelerating 3D CNN-based Lung Nodule Segmentation on a Multi-FPGA
System},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {117},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293935},
doi = {10.1145/3289602.3293935},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/ShenWHWZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ShenX19,
author = {Minghua Shen and
Nong Xiao},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Parrot: {A} More Effective Parallel Routing Approach to FPGAs},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {119},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293944},
doi = {10.1145/3289602.3293944},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/ShenX19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ShererFLL19,
author = {Zachary Sherer and
Eric Finnerty and
Yan Luo and
Hang Liu},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Software Hardware Co-Optimized {BFS} on FPGAs},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {190},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293982},
doi = {10.1145/3289602.3293982},
timestamp = {Fri, 21 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/ShererFLL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ShiLGKZ19,
author = {Feng Shi and
Haochen Li and
Yuhe Gao and
Benjamin Kuschner and
Song{-}Chun Zhu},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Sparse Winograd Convolutional Neural Networks on Small-scale Systolic
Arrays},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {118},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293939},
doi = {10.1145/3289602.3293939},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/ShiLGKZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/SwarbrickGAGA19,
author = {Ian Swarbrick and
Dinesh Gaitonde and
Sagheer Ahmad and
Brian Gaide and
Ygal Arbel},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Network-on-Chip Programmable Platform in Versal\({}^{\mbox{TM}}\)
{ACAP} Architecture},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {212--221},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293908},
doi = {10.1145/3289602.3293908},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/SwarbrickGAGA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/TaheriBBVN19,
author = {Sajjad Taheri and
Payman Behnam and
Eli Bozorgzadeh and
Alexander V. Veidenbaum and
Alexandru Nicolau},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {{AFFIX:} Automatic Acceleration Framework for {FPGA} Implementation
of OpenVX Vision Algorithms},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {252--261},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293907},
doi = {10.1145/3289602.3293907},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/TaheriBBVN19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/TangL019,
author = {Zhucheng Tang and
Guojie Luo and
Ming Jiang},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {FTConv: {FPGA} Acceleration for Transposed Convolution Layers in Deep
Neural Networks},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {189},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293976},
doi = {10.1145/3289602.3293976},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/TangL019.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/TianS19,
author = {Shanquan Tian and
Jakub Szefer},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Temporal Thermal Covert Channels in Cloud FPGAs},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {298--303},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293920},
doi = {10.1145/3289602.3293920},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/TianS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/TuricuCV19,
author = {Dan Cristian Turicu and
Octavian Cret and
Lucia Vacariu},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Storage Mirroring for Bare-Metal Systems on {FPGA} Devices},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {304--305},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293985},
doi = {10.1145/3289602.3293985},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/TuricuCV19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/Vissers19,
author = {Kees A. Vissers},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Versal: The Xilinx Adaptive Compute Acceleration Platform {(ACAP)}},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {83},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3294007},
doi = {10.1145/3289602.3294007},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/Vissers19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/VogelSGA19,
author = {Sebastian Vogel and
Jannik Springer and
Andre Guntoro and
Gerd Ascheid},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Efficient Acceleration of CNNs for Semantic Segmentation on FPGAs},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {309},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3294006},
doi = {10.1145/3289602.3294006},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/VogelSGA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/Wei0ZYC19,
author = {Xuechao Wei and
Yun Liang and
Peng Zhang and
Cody Hao Yu and
Jason Cong},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Overcoming Data Transfer Bottlenecks in {DNN} Accelerators via Layer-Conscious
Memory Managment},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {120},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293947},
doi = {10.1145/3289602.3293947},
timestamp = {Wed, 30 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/Wei0ZYC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/WijeratneEJRP19,
author = {Sasindu Wijeratne and
Ashen Ekanayake and
Sandaruwan Jayaweera and
Danuka Ravishan and
Ajith Pasqual},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Scalable High Performance {SDN} Switch Architecture on {FPGA} for
Core Networks},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {117},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293933},
doi = {10.1145/3289602.3293933},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/WijeratneEJRP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/WuZBCT19,
author = {Ephrem Wu and
Xiaoqian Zhang and
David Berman and
Inkeun Cho and
John Thendean},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Compute-Efficient Neural-Network Acceleration},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {191--200},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293925},
doi = {10.1145/3289602.3293925},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/WuZBCT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/XieL19,
author = {Jiafeng Xie and
Chiou{-}Yng Lee},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Embracing Systolic: Super Systolization of Large-Scale Circulant Matrix-vector
Multiplication on {FPGA} with Subquadratic Space Complexity},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {187},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293968},
doi = {10.1145/3289602.3293968},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/XieL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/XingLSZQJLWSW19,
author = {Yu Xing and
Shuang Liang and
Lingzhi Sui and
Zhen Zhang and
Jiantao Qiu and
Xijie Jia and
Xin Liu and
Yushun Wang and
Yi Shan and
Yu Wang},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {{DNNVM:} End-to-End Compiler Leveraging Operation Fusion on FPGA-based
{CNN} Accelerators},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {187--188},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293972},
doi = {10.1145/3289602.3293972},
timestamp = {Wed, 21 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/XingLSZQJLWSW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/YanLLYW19,
author = {Hui Yan and
Zhaoshi Li and
Leibo Liu and
Shouyi Yin and
Shaojun Wei},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Constructing Concurrent Data Structures on {FPGA} with Channels},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {172--177},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293921},
doi = {10.1145/3289602.3293921},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/YanLLYW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/YangHWZ0GBLVWK19,
author = {Yifan Yang and
Qijing Huang and
Bichen Wu and
Tianjun Zhang and
Liang Ma and
Giulio Gambardella and
Michaela Blott and
Luciano Lavagno and
Kees A. Vissers and
John Wawrzynek and
Kurt Keutzer},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on
Embedded FPGAs},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {23--32},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293902},
doi = {10.1145/3289602.3293902},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/YangHWZ0GBLVWK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/YangWMYA19,
author = {Fan Yang and
Zhan Wang and
Xiaoxiao Ma and
Guojun Yuan and
Xuejun An},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {SwitchAgg: {A} Further Step Towards In-Network Computation},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {185},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293963},
doi = {10.1145/3289602.3293963},
timestamp = {Tue, 12 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/YangWMYA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/YouW19,
author = {Weijie You and
Chang Wu},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {A Reconfigurable Accelerator for Sparse Convolutional Neural Networks},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {119},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293945},
doi = {10.1145/3289602.3293945},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/YouW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ZandD19,
author = {Ramtin Zand and
Ronald F. DeMara},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {{HSC-FPGA}},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {118--119},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293940},
doi = {10.1145/3289602.3293940},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/ZandD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ZengLLKXSHWY19,
author = {Shulin Zeng and
Yujun Lin and
Shuang Liang and
Junlong Kang and
Dongliang Xie and
Yi Shan and
Song Han and
Yu Wang and
Huazhong Yang},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {A Fine-Grained Sparse Accelerator for Multi-Precision {DNN}},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {185},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293964},
doi = {10.1145/3289602.3293964},
timestamp = {Wed, 21 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/ZengLLKXSHWY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ZhangC0BX19,
author = {Ke Zhang and
Yisong Chang and
Mingyu Chen and
Yungang Bao and
Zhiwei Xu},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Engaging Heterogeneous FPGAs in the Cloud},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {308},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3294001},
doi = {10.1145/3289602.3294001},
timestamp = {Sun, 19 Feb 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/ZhangC0BX19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ZhangL19,
author = {Jialiang Zhang and
Jing Li},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Unleashing the Power of Soft Logic for Convolutional Neural Network
Acceleration via Product Quantization},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {120},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293951},
doi = {10.1145/3289602.3293951},
timestamp = {Thu, 05 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/ZhangL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/fpga/ZhouVS19,
author = {Yun Zhou and
Dries Vercruyce and
Dirk Stroobandt},
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {{MODA-PSO:} Towards Fast Hard Block Legalization for Analytical {FPGA}
Placement},
booktitle = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
pages = {184},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602.3293959},
doi = {10.1145/3289602.3293959},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/fpga/ZhouVS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/fpga/2019,
editor = {Kia Bazargan and
Stephen Neuendorffer},
title = {Proceedings of the 2019 {ACM/SIGDA} International Symposium on Field-Programmable
Gate Arrays, {FPGA} 2019, Seaside, CA, USA, February 24-26, 2019},
publisher = {{ACM}},
year = {2019},
url = {https://doi.org/10.1145/3289602},
doi = {10.1145/3289602},
isbn = {978-1-4503-6137-8},
timestamp = {Tue, 05 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/fpga/2019.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
retrieved on 2024-04-19 15:43 CEST from data curated by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
