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@inproceedings{DBLP:conf/patmos/AbboKCS04,
author = {Anteneh A. Abbo and
Richard P. Kleihorst and
Vishal Choudhary and
Leo Sevat},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Power Consumption of Performance-Scaled {SIMD} Processors},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {532--540},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_55},
doi = {10.1007/978-3-540-30205-6\_55},
timestamp = {Tue, 14 May 2019 10:00:54 +0200},
biburl = {https://dblp.org/rec/conf/patmos/AbboKCS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/AnderssonSL04,
author = {Daniel A. Andersson and
Lars J. Svensson and
Per Larsson{-}Edefors},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {On Skin Effect in On-Chip Interconnects},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {463--470},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_48},
doi = {10.1007/978-3-540-30205-6\_48},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/AnderssonSL04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/Arnold04,
author = {Mark G. Arnold},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {{LPVIP:} {A} Low-Power ROM-Less {ALU} for Low-Precision {LNS}},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {675--684},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_69},
doi = {10.1007/978-3-540-30205-6\_69},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/Arnold04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/AtienzaMCMS04,
author = {David Atienza and
Stylianos Mamagkakis and
Francky Catthoor and
Jose Manuel Mendias and
Dimitrios Soudris},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Modular Construction and Power Modelling of Dynamic Memory Managers
for Embedded Systems},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {510--520},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_53},
doi = {10.1007/978-3-540-30205-6\_53},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/AtienzaMCMS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/BastianLGR04,
author = {Fabricio B. Bastian and
Cristiano Lazzari and
Jos{\'{e}} Lu{\'{\i}}s Almada G{\"{u}}ntzel and
Ricardo Reis},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {A New Transistor Folding Algorithm Applied to an Automatic Full-Custom
Layout Generation Tool},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {732--741},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_75},
doi = {10.1007/978-3-540-30205-6\_75},
timestamp = {Tue, 22 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/BastianLGR04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/BjerregaardMS04,
author = {Tobias Bjerregaard and
Shankar Mahadevan and
Jens Spars{\o}},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode
Modeling},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {301--310},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_32},
doi = {10.1007/978-3-540-30205-6\_32},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/BjerregaardMS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/BonaZZ04,
author = {Andrea Bona and
Vittorio Zaccaria and
Roberto Zafalon},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Low Effort, High Accuracy Network-on-Chip Power Macro Modeling},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {541--552},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_56},
doi = {10.1007/978-3-540-30205-6\_56},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/BonaZZ04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/BrandoleseFS04,
author = {Carlo Brandolese and
William Fornaciari and
Fabio Salice},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Discrete-Event Modeling and Simulation of Superscalar Microprocessor
Architectures},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {238--247},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_26},
doi = {10.1007/978-3-540-30205-6\_26},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/BrandoleseFS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/BucciGLT04,
author = {Marco Bucci and
Michele Guglielmo and
Raimondo Luzzi and
Alessandro Trifiletti},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {A Power Consumption Randomization Countermeasure for DPA-Resistant
Cryptographic Processors},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {481--490},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_50},
doi = {10.1007/978-3-540-30205-6\_50},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/BucciGLT04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/CaputaFHAAS04,
author = {Peter Caputa and
Henrik Fredriksson and
Martin Hansson and
Stefan Back Andersson and
Atila Alvandpour and
Christer Svensson},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {An Extended Transition Energy Cost Model for Buses in Deep Submicron
Technologies},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {849--858},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_87},
doi = {10.1007/978-3-540-30205-6\_87},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/CaputaFHAAS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/CelinskiAC04,
author = {Peter Celinski and
Derek Abbott and
Sorin Cotofana},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Delay Evaluation of High Speed Data-Path Circuits Based on Threshold
Logic},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {899--906},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_92},
doi = {10.1007/978-3-540-30205-6\_92},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/CelinskiAC04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/ChangQS04,
author = {Hongliang Chang and
Haifeng Qian and
Sachin S. Sapatnekar},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {The Certainty of Uncertainty: Randomness in Nanometer Design},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {36--47},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_6},
doi = {10.1007/978-3-540-30205-6\_6},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/ChangQS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/ChenO04,
author = {Howard Chen and
Daniel L. Ostapko},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Modeling Temporal and Spatial Power Supply Voltage Variation for Timing
Analysis},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {809--818},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_83},
doi = {10.1007/978-3-540-30205-6\_83},
timestamp = {Fri, 24 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/ChenO04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/CservenyMP04,
author = {Stefan Cserveny and
Jean{-}Marc Masgonty and
Christian Piguet},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Noise Margin in Low Power {SRAM} Cells},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {889--898},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_91},
doi = {10.1007/978-3-540-30205-6\_91},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/CservenyMP04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/DagaPCRS04,
author = {Jean Michel Daga and
Caroline Papaix and
Marylene Combe and
Emmanuel Racape and
Vincent Sialelli},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Embedded {EEPROM} Speed Optimization Using System Power Supply Resources},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {381--391},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_40},
doi = {10.1007/978-3-540-30205-6\_40},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/DagaPCRS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/Dallavalle04,
author = {Carlo Dallavalle},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Adaptive Subthreshold Leakage Reduction Through {N/P} Wells Reverse
Biasing},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {16},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_4},
doi = {10.1007/978-3-540-30205-6\_4},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/Dallavalle04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/DimitrakopoulosKKN04,
author = {Giorgos Dimitrakopoulos and
Pavlos Kolovos and
P. Kalogerakis and
Dimitris Nikolos},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Design of High-Speed Low-Power Parallel-Prefix {VLSI} Adders},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {248--257},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_27},
doi = {10.1007/978-3-540-30205-6\_27},
timestamp = {Fri, 15 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/DimitrakopoulosKKN04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/DoLB04,
author = {Minh Quang Do and
Per Larsson{-}Edefors and
Lars Bengtsson},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Table-Based Total Power Consumption Estimation of Memory Arrays for
Architects},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {869--878},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_89},
doi = {10.1007/978-3-540-30205-6\_89},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/DoLB04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/DragoneQBG04,
author = {Nicola Dragone and
Michele Quarantelli and
Massimo Bertoletti and
Carlo Guardiani},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {High Yield Standard Cell Libraries: Optimization and Modeling},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {129--137},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_15},
doi = {10.1007/978-3-540-30205-6\_15},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/DragoneQBG04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/DrososBMBT04,
author = {Christos Drosos and
Labros Bisdounis and
Dimitris Metafas and
Spyros Blionas and
Anna Tatsaki},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {A Multi-level Validation Methodology for Wireless Network Applications},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {332--341},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_35},
doi = {10.1007/978-3-540-30205-6\_35},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/DrososBMBT04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/FischerABTGS04,
author = {J{\"{u}}rgen Fischer and
Ettore Amirante and
Agnese Bargagli{-}Stoffi and
Philip Teichmann and
Dominik Gruber and
Doris Schmitt{-}Landsiedel},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Power Supply Net for Adiabatic Circuits},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {413--422},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_43},
doi = {10.1007/978-3-540-30205-6\_43},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/FischerABTGS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/FrankG04,
author = {Uri Frank and
Ran Ginosar},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {A Predictive Synchronizer for Periodic Clock Domains},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {402--412},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_42},
doi = {10.1007/978-3-540-30205-6\_42},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/FrankG04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/FuLHCTP04,
author = {Jingjing Fu and
Zuying Luo and
Xianlong Hong and
Yici Cai and
Sheldon X.{-}D. Tan and
Zhu Pan},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for
Robust On-Chip Power Delivery},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {433--441},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_45},
doi = {10.1007/978-3-540-30205-6\_45},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/FuLHCTP04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/FukuokaIHNT04,
author = {Kazuki Fukuoka and
Masaaki Iijima and
Kenji Hamada and
Masahiro Numa and
Akira Tada},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied
{PD-SOI}},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {423--432},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_44},
doi = {10.1007/978-3-540-30205-6\_44},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/FukuokaIHNT04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/GalanisTTSG04,
author = {Michalis D. Galanis and
George Theodoridis and
Spyros Tragoudas and
Dimitrios Soudris and
Constantinos E. Goutis},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Mapping Computational Intensive Applications to a New Coarse-Grained
Reconfigurable Data-Path},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {652--661},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_67},
doi = {10.1007/978-3-540-30205-6\_67},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/GalanisTTSG04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/GemmekeN04,
author = {Tobias Gemmeke and
Tobias G. Noll},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {A Physically Oriented Model to Quantify the Noise-on-Delay Effect},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {879--888},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_90},
doi = {10.1007/978-3-540-30205-6\_90},
timestamp = {Thu, 15 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/GemmekeN04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/Guitton-OuhamouFBN04,
author = {Patricia Guitton{-}Ouhamou and
Hanene Ben Fradj and
C{\'{e}}cile Belleudy and
Michel Auguin},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Low Power Co-design Tool and Power Optimization of Schedules and Memory
System},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {603--612},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_62},
doi = {10.1007/978-3-540-30205-6\_62},
timestamp = {Thu, 13 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/Guitton-OuhamouFBN04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/HassouneNLF04,
author = {Ilham Hassoune and
Amaury N{\`{e}}ve and
Jean{-}Didier Legat and
Denis Flandre},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid
Full-Adder Cell},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {189--197},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_21},
doi = {10.1007/978-3-540-30205-6\_21},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/HassouneNLF04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/HelmsSN04,
author = {Domenik Helms and
Eike Schmidt and
Wolfgang Nebel},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Leakage in {CMOS} Circuits - An Introduction},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {17--35},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_5},
doi = {10.1007/978-3-540-30205-6\_5},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/HelmsSN04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/HenzlerGBS04,
author = {Stephan Henzler and
Georg Georgakos and
J{\"{o}}rg Berthold and
Doris Schmitt{-}Landsiedel},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop
with Low Power and Area Consumption},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {392--401},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_41},
doi = {10.1007/978-3-540-30205-6\_41},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/HenzlerGBS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/HenzlerGBS04a,
author = {Stephan Henzler and
Georg Georgakos and
J{\"{o}}rg Berthold and
Doris Schmitt{-}Landsiedel},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Two Level Compact Simulation Methodology for Timing Analysis of Power-Switched
Circuits},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {789--798},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_81},
doi = {10.1007/978-3-540-30205-6\_81},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/HenzlerGBS04a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/ItohOK04,
author = {Kiyoo Itoh and
Kenichi Osada and
Takayuki Kawahara},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Low-Voltage Embedded RAMs - Current Status and Future Trends},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {3--15},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_3},
doi = {10.1007/978-3-540-30205-6\_3},
timestamp = {Thu, 07 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/ItohOK04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/JayapalaABCCD04,
author = {Murali Jayapala and
Tom Vander Aa and
Francisco Barat and
Francky Catthoor and
Henk Corporaal and
Geert Deconinck},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {{L0} Cluster Synthesis and Operation Shuffling},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {311--321},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_33},
doi = {10.1007/978-3-540-30205-6\_33},
timestamp = {Mon, 05 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/JayapalaABCCD04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/JohanssonGW04,
author = {Kenny Johansson and
Oscar Gustafsson and
Lars Wanhammar},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Power Estimation for Ripple-Carry Adders with Correlated Input Data},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {662--674},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_68},
doi = {10.1007/978-3-540-30205-6\_68},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/JohanssonGW04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/JuniorMBC04,
author = {Meuse N. Oliveira Jr. and
Paulo Romero Martins Maciel and
Raimundo S. Barreto and
Fernando F. Carvalho},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Towards a Software Power Cost Analysis Framework Using Colored Petri
Net},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {362--371},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_38},
doi = {10.1007/978-3-540-30205-6\_38},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/JuniorMBC04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/KakarountasSNG04,
author = {Athanasios Kakarountas and
Vassilis Spiliotopoulos and
Spiridon Nikolaidis and
Constantinos E. Goutis},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {The Impact of Low-Power Techniques on the Design of Portable Safety-Critical
Systems},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {501--509},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_52},
doi = {10.1007/978-3-540-30205-6\_52},
timestamp = {Tue, 04 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/KakarountasSNG04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/Kanopoulos04,
author = {Nick Kanopoulos},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Design Methodology for Rapid Development of SoC ICs Based on an Innovative
System Architecture with Emphasis to Timing Closure and Power Consumption
Optimization},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {2},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_2},
doi = {10.1007/978-3-540-30205-6\_2},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/Kanopoulos04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/KaratasosKTG04,
author = {Dimitris Karatasos and
Athanasios Kakarountas and
George Theodoridis and
Constantinos E. Goutis},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {A Novel Constant-Time Fault-Secure Binary Counter},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {742--749},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_76},
doi = {10.1007/978-3-540-30205-6\_76},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/KaratasosKTG04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/KavvadiasN04,
author = {Nikolaos Kavvadias and
Spiridon Nikolaidis},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Application Analysis with Integrated Identification of Complex Instructions
for Configurable Processors},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {633--642},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_65},
doi = {10.1007/978-3-540-30205-6\_65},
timestamp = {Tue, 04 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/KavvadiasN04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/KayaSOB04,
author = {Idris Kaya and
Silke Salewski and
Markus Olbrich and
Erich Barke},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Wirelength Reduction Using 3-D Physical Design},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {453--462},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_47},
doi = {10.1007/978-3-540-30205-6\_47},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/KayaSOB04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/KhanAE04,
author = {Zahid Khan and
Tughrul Arslan and
Ahmet T. Erdogan},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {A Dual Low Power and Crosstalk Immune Encoding Scheme for System-on-Chip
Buses},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {585--592},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_60},
doi = {10.1007/978-3-540-30205-6\_60},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/patmos/KhanAE04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/KinaneMOMM04,
author = {Andrew Kinane and
Valentin Muresan and
Noel E. O'Connor and
Noel Murphy and
Se{\'{a}}n Marlow},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Energy-Efficient Hardware Architecture for Variable N-point 1D {DCT}},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {780--788},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_80},
doi = {10.1007/978-3-540-30205-6\_80},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/KinaneMOMM04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/KinnimentY04,
author = {D. J. Kinniment and
Alexandre Yakovlev},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Low Latency Synchronization Through Speculation},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {278--288},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_30},
doi = {10.1007/978-3-540-30205-6\_30},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/KinnimentY04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/KretzschmarBM04,
author = {Claudia Kretzschmar and
Torsten Bitterlich and
Dietmar M{\"{u}}ller},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {A High-Level {DSM} Bus Model for Accurate Exploration of Transmission
Behaviour and Power Estimation of Global System Buses},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {90--99},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_11},
doi = {10.1007/978-3-540-30205-6\_11},
timestamp = {Sat, 04 Aug 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/KretzschmarBM04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/KrsticG04,
author = {Milos Krstic and
Eckhard Grass},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {GALSification of {IEEE} 802.11a Baseband Processor},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {258--267},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_28},
doi = {10.1007/978-3-540-30205-6\_28},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/patmos/KrsticG04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/LandraultAMRA04,
author = {A. Landrault and
Nadine Az{\'{e}}mard and
Philippe Maurine and
Michel Robert and
Daniel Auvergne},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Design Optimization with Automated Cell Generation},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {722--731},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_74},
doi = {10.1007/978-3-540-30205-6\_74},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/LandraultAMRA04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/LasbouyguesWMAA04,
author = {B. Lasbouygues and
Robin Wilson and
Philippe Maurine and
Nadine Az{\'{e}}mard and
Daniel Auvergne},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Temperature Dependence in Low Power {CMOS} {UDSM} Process},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {110--118},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_13},
doi = {10.1007/978-3-540-30205-6\_13},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/LasbouyguesWMAA04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/LasbouyguesWMAA04a,
author = {B. Lasbouygues and
Robin Wilson and
Philippe Maurine and
Nadine Az{\'{e}}mard and
Daniel Auvergne},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Physical Extension of the Logical Effort Model},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {838--848},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_86},
doi = {10.1007/978-3-540-30205-6\_86},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/LasbouyguesWMAA04a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/LattanziAB04,
author = {Emanuele Lattanzi and
Andrea Acquaviva and
Alessandro Bogliolo},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Run-Time Software Monitor of the Power Consumption of Wireless Network
Interface Cards},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {352--361},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_37},
doi = {10.1007/978-3-540-30205-6\_37},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/LattanziAB04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/LeungTH04,
author = {Lap{-}Fai Leung and
Chi{-}Ying Tsui and
Xiaobo Sharon Hu},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Exploiting Dynamic Workload Variation in Offline Low Energy Voltage
Scheduling},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {553--563},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_57},
doi = {10.1007/978-3-540-30205-6\_57},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/LeungTH04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/LiuF04,
author = {Yijun Liu and
Stephen B. Furber},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Minimizing the Power Consumption of an Asynchronous Multiplier},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {289--300},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_31},
doi = {10.1007/978-3-540-30205-6\_31},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/LiuF04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/LopezGC04,
author = {Sonia L{\'{o}}pez and
Oscar Garnica and
Jos{\'{e}} Manuel Colmenar},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Enhancing {GALS} Processor Performance Using Data Classification Based
on Data Latency},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {623--632},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_64},
doi = {10.1007/978-3-540-30205-6\_64},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/LopezGC04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/MailiDS04,
author = {Alexander Maili and
Damian Dalton and
Christian Steger},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {A Generic Timing Mechanism for Using the {APPLES} Gate-Level Simulator
in a Mixed-Level Simulation Environment},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {799--808},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_82},
doi = {10.1007/978-3-540-30205-6\_82},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/MailiDS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/Man04,
author = {Hugo De Man},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Connecting E-Dreams to Deep-Submicron Realities},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {1},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_1},
doi = {10.1007/978-3-540-30205-6\_1},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/Man04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/ManzakC04,
author = {Ali Manzak and
Chaitali Chakrabarti},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Optimum Buffer Size for Dynamic Voltage Processors},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {711--721},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_73},
doi = {10.1007/978-3-540-30205-6\_73},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/ManzakC04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/MasselosBMFSN04,
author = {Kostas Masselos and
Spyros Blionas and
Jean{-}Yves Mignolet and
A. Foster and
Dimitrios Soudris and
Spiridon Nikolaidis},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Hardware Building Blocks of a Mixed Granularity Reconfigurable System-on-Chip
Platform},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {613--622},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_63},
doi = {10.1007/978-3-540-30205-6\_63},
timestamp = {Tue, 04 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/MasselosBMFSN04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/MerrettA04,
author = {Geoff V. Merrett and
Bashir M. Al{-}Hashimi},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Leakage Power Analysis and Comparison of Deep Submicron Logic Gates},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {198--207},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_22},
doi = {10.1007/978-3-540-30205-6\_22},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/MerrettA04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/MichelVMAA04,
author = {Xavier Michel and
Alexandre Verle and
Philippe Maurine and
Nadine Az{\'{e}}mard and
Daniel Auvergne},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Performance Metric Based Optimization Protocol},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {100--109},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_12},
doi = {10.1007/978-3-540-30205-6\_12},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/MichelVMAA04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/MillanJBRGO04,
author = {Alejandro Mill{\'{a}}n and
Jorge Juan{-}Chico and
Manuel J. Bellido and
Paulino Ruiz{-}de{-}Clavijo and
David Guerrero Martos and
Enrique Ost{\'{u}}a},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Signal Sampling Based Transition Modeling for Digital Gates Characterization},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {829--837},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_85},
doi = {10.1007/978-3-540-30205-6\_85},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/patmos/MillanJBRGO04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/MohsenH04,
author = {Amjad Mohsen and
Richard Hofmann},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Power Modeling, Estimation, and Optimization for Automated Co-design
of Real-Time Embedded Systems},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {643--651},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_66},
doi = {10.1007/978-3-540-30205-6\_66},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/MohsenH04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/MullerWMS04,
author = {Matthias M{\"{u}}ller and
Andreas Wortmann and
Dominik Mader and
Sven Simon},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Register Isolation for Synthesizable Register Files},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {228--237},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_25},
doi = {10.1007/978-3-540-30205-6\_25},
timestamp = {Fri, 27 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/patmos/MullerWMS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/MurganOSZPG04,
author = {Tudor Murgan and
Alberto Garc{\'{\i}}a Ortiz and
Clemens Schlachta and
Heiko Zimmer and
Mihail Petrov and
Manfred Glesner},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {On Timing and Power Consumption in Inductively Coupled On-Chip Interconnects},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {819--828},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_84},
doi = {10.1007/978-3-540-30205-6\_84},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/MurganOSZPG04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/NeffeRSWRM04,
author = {Ulrich Neffe and
Klaus Rothbart and
Christian Steger and
Reinhold Weiss and
Edgar Rieger and
Andreas M{\"{u}}hlberger},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {A Flexible and Accurate Energy Model of an Instruction-Set Simulator
for Secure Smart Card Software Design},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {491--500},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_51},
doi = {10.1007/978-3-540-30205-6\_51},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/NeffeRSWRM04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/NieuwlandKM04,
author = {Andr{\'{e}} K. Nieuwland and
Atul Katoch and
Maurice Meijer},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Reducing Cross-Talk Induced Power Consumption and Delay},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {179--188},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_20},
doi = {10.1007/978-3-540-30205-6\_20},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/NieuwlandKM04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/OhH04,
author = {Myeong{-}Hoon Oh and
Dong{-}Soo Har},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {A Novel Mechanism for Delay-Insensitive Data Transfer Based on Current-Mode
Multiple Valued Logic},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {691--700},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_71},
doi = {10.1007/978-3-540-30205-6\_71},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/OhH04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/OlivieriSST04,
author = {Mauro Olivieri and
Mirko Scarana and
Giuseppe Scotti and
Alessandro Trifiletti},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Yield Optimization by Means of Process Parameters Estimation: Comparison
Between {ABB} and {ASV} Techniques},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {119--128},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_14},
doi = {10.1007/978-3-540-30205-6\_14},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/OlivieriSST04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/OlsenBK04,
author = {Anders Br{\o}dl{\o}s Olsen and
Finn B{\"{u}}ttner and
Peter Koch},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {On Combined {DVS} and Processor Evaluation},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {322--331},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_34},
doi = {10.1007/978-3-540-30205-6\_34},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/OlsenBK04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/OrtizMG04,
author = {Alberto Garc{\'{\i}}a Ortiz and
Tudor Murgan and
Manfred Glesner},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Moment-Based Estimation of Switching Activity for Correlated Distributions},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {859--868},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_88},
doi = {10.1007/978-3-540-30205-6\_88},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/OrtizMG04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/PalermoS04,
author = {Gianluca Palermo and
Cristina Silvano},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {{PIRATE:} {A} Framework for Power/Performance Exploration of Network-on-Chip
Architectures},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {521--531},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_54},
doi = {10.1007/978-3-540-30205-6\_54},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/PalermoS04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/ParkMP04,
author = {Jun{-}Cheol Park and
Vincent John Mooney III and
Philipp Pfeiffenberger},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Sleepy Stack Reduction of Leakage Power},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {148--158},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_17},
doi = {10.1007/978-3-540-30205-6\_17},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/ParkMP04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/PessolanoM04,
author = {Francesco Pessolano and
R. I. M. P. Meijer},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {A 260ps Quasi-static {ALU} in 90nm {CMOS}},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {372--380},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_39},
doi = {10.1007/978-3-540-30205-6\_39},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/PessolanoM04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/RenG04,
author = {Jihong Ren and
Mark R. Greenstreet},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Crosstalk Cancellation for Realistic {PCB} Buses},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {48--57},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_7},
doi = {10.1007/978-3-540-30205-6\_7},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/RenG04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/RuanA04,
author = {Jie Ruan and
Mark G. Arnold},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Threshold Mean Larger Ratio Motion Estimation in {MPEG} Encoding Using
{LNS}},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {208--217},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_23},
doi = {10.1007/978-3-540-30205-6\_23},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/RuanA04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/RusuBIT04,
author = {Ana Rusu and
Alexei Borodenkov and
Mohammed Ismail and
Hannu Tenhunen},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Design of a Power/Performance Efficient Single-Loop Sigma-Delta Modulator
for Wireless Receivers},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {564--573},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_58},
doi = {10.1007/978-3-540-30205-6\_58},
timestamp = {Mon, 23 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/patmos/RusuBIT04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/SalernoMP04,
author = {Sabino Salerno and
Enrico Macii and
Massimo Poncino},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {A Low-Power Encoding Scheme for GigaByte Video Interfaces},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {58--68},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_8},
doi = {10.1007/978-3-540-30205-6\_8},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/SalernoMP04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/SchusterNPF04,
author = {Christian Schuster and
Jean{-}Luc Nagel and
Christian Piguet and
Pierre{-}Andr{\'{e}} Farine},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Leakage Reduction at the Architectural Level and Its Application to
16 Bit Multiplier Architectures},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {169--178},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_19},
doi = {10.1007/978-3-540-30205-6\_19},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/SchusterNPF04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/SennLJM04,
author = {Eric Senn and
Johann Laurent and
Nathalie Julien and
Eric Martin},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {SoftExplorer: Estimation, Characterization, and Optimization of the
Power and Energy Consumption at the Algorithmic Level},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {342--351},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_36},
doi = {10.1007/978-3-540-30205-6\_36},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/SennLJM04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/ShangBBKSY04,
author = {Delong Shang and
Frank P. Burns and
Alexandre V. Bystrov and
Albert Koelmans and
Danil Sokolov and
Alexandre Yakovlev},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {A Low and Balanced Power Implementation of the {AES} Security Mechanism
Using Self-Timed Circuits},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {471--480},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_49},
doi = {10.1007/978-3-540-30205-6\_49},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/ShangBBKSY04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/SlimaniRSR04,
author = {Kamel Slimani and
Yann R{\'{e}}mond and
Gilles Sicard and
Marc Renaudin},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {{TAST} Profiler and Low Energy Asynchronous Design Methodology},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {268--277},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_29},
doi = {10.1007/978-3-540-30205-6\_29},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/SlimaniRSR04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/SonN04,
author = {Y. S. Son and
Jong Whoa Na},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {A New Logic Transformation Method for Both Low Power and High Testability},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {770--779},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_79},
doi = {10.1007/978-3-540-30205-6\_79},
timestamp = {Sun, 03 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/SonN04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/SongPKC04,
author = {Eunseok Song and
Young{-}Kil Park and
Soon Kwon and
Soo{-}Ik Chae},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {A Cycle-Accurate Energy Estimator for {CMOS} Digital Circuits},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {159--168},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_18},
doi = {10.1007/978-3-540-30205-6\_18},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/SongPKC04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/StanZ04,
author = {Mircea R. Stan and
Yan Zhang},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Perfect 3-Limited-Weight Code for Low Power {I/O}},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {79--89},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_10},
doi = {10.1007/978-3-540-30205-6\_10},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/StanZ04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/SutterDBB04,
author = {Gustavo Sutter and
Jean{-}Pierre Deschamps and
Gery Bioul and
Eduardo I. Boemo},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Power Aware Dividers in {FPGA}},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {574--584},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_59},
doi = {10.1007/978-3-540-30205-6\_59},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/SutterDBB04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/TahedlP04,
author = {Markus Tahedl and
Hans{-}J{\"{o}}rg Pfleiderer},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Dynamic Wire Delay and Slew Metrics for Integrated Bus Structures},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {69--78},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_9},
doi = {10.1007/978-3-540-30205-6\_9},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/TahedlP04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/TruccoBL04,
author = {Gabriella Trucco and
Giorgio Boselli and
Valentino Liberali},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {A Study of Crosstalk Through Bonding and Package Parasitics in {CMOS}
Mixed Analog-Digital Circuits},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {138--147},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_16},
doi = {10.1007/978-3-540-30205-6\_16},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/TruccoBL04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/Valencia04,
author = {Leonardo Valencia},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Low Level Adaptive Frequency in Synthesis of High Speed Digital Circuits},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {685--690},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_70},
doi = {10.1007/978-3-540-30205-6\_70},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/Valencia04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/VassiliadisCKN04,
author = {Nikolaos Vassiliadis and
A. Chormoviti and
Nikolaos Kavvadias and
Spiridon Nikolaidis},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {The Effect of Data-Reuse Transformations on Multimedia Applications
for Different Processing Platforms},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {593--602},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_61},
doi = {10.1007/978-3-540-30205-6\_61},
timestamp = {Tue, 04 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/VassiliadisCKN04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/VelenisF04,
author = {Dimitrios Velenis and
Eby G. Friedman},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Buffer Sizing for Crosstalk Induced Delay Uncertainty},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {750--759},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_77},
doi = {10.1007/978-3-540-30205-6\_77},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/VelenisF04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/VouzisP04,
author = {Panagiotis D. Vouzis and
Vassilis Paliouras},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Optimal Logarithmic Representation in Terms of {SNR} Behavior},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {760--769},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_78},
doi = {10.1007/978-3-540-30205-6\_78},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/VouzisP04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/WangHJYHY04,
author = {Yin Wang and
Xianlong Hong and
Tong Jing and
Yang Yang and
Xiaodong Hu and
Guiying Yan},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {An Efficient Low-Degree {RMST} Algorithm for {VLSI/ULSI} Physical
Design},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {442--452},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_46},
doi = {10.1007/978-3-540-30205-6\_46},
timestamp = {Thu, 26 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/WangHJYHY04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/WelligZW04,
author = {Armin Wellig and
Julien Zory and
Norbert Wehn},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Energy- and Area-Efficient Deinterleaving Architecture for High-Throughput
Wireless Applications},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {218--227},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_24},
doi = {10.1007/978-3-540-30205-6\_24},
timestamp = {Fri, 26 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/WelligZW04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/YangCCP04,
author = {Jing{-}Ling Yang and
Oliver Chiu{-}sing Choy and
Cheong{-}Fat Chan and
Kong{-}Pang Pun},
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Pipelines in Dynamic Dual-Rail Circuits},
booktitle = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
pages = {701--710},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/978-3-540-30205-6\_72},
doi = {10.1007/978-3-540-30205-6\_72},
timestamp = {Mon, 04 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/YangCCP04.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/patmos/2004,
editor = {Enrico Macii and
Odysseas G. Koufopavlou and
Vassilis Paliouras},
title = {Integrated Circuit and System Design, Power and Timing Modeling, Optimization
and Simulation; 14th International Workshop, {PATMOS} 2004, Santorini,
Greece, September 15-17, 2004, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {3254},
publisher = {Springer},
year = {2004},
url = {https://doi.org/10.1007/b100662},
doi = {10.1007/B100662},
isbn = {3-540-23095-5},
timestamp = {Tue, 14 May 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/2004.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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