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@inproceedings{DBLP:conf/slip/Banerjee09,
  author       = {Kaustav Banerjee},
  editor       = {Chung{-}Kuan Cheng and
                  Sherief Reda},
  title        = {Graphene based nanomaterials for {VLSI} interconnect and energy-storage
                  applications},
  booktitle    = {The 11th International Workshop on System-Level Interconnect Prediction
                  {(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
  pages        = {105--106},
  publisher    = {{ACM}},
  year         = {2009},
  url          = {https://doi.org/10.1145/1572471.1572490},
  doi          = {10.1145/1572471.1572490},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/Banerjee09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/Bottoms09,
  author       = {Bill R. Bottoms},
  editor       = {Chung{-}Kuan Cheng and
                  Sherief Reda},
  title        = {Interconnect solutions for TeraScale computing},
  booktitle    = {The 11th International Workshop on System-Level Interconnect Prediction
                  {(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
  pages        = {1--2},
  publisher    = {{ACM}},
  year         = {2009},
  url          = {https://doi.org/10.1145/1572471.1572472},
  doi          = {10.1145/1572471.1572472},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/Bottoms09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/CessnaB09,
  author       = {Joseph B. Cessna and
                  Thomas R. Bewley},
  editor       = {Chung{-}Kuan Cheng and
                  Sherief Reda},
  title        = {Honeycomb-structured computational interconnects and their scalable
                  extension to spherical domains},
  booktitle    = {The 11th International Workshop on System-Level Interconnect Prediction
                  {(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
  pages        = {27--36},
  publisher    = {{ACM}},
  year         = {2009},
  url          = {https://doi.org/10.1145/1572471.1572477},
  doi          = {10.1145/1572471.1572477},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/CessnaB09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/CongCRT09,
  author       = {Jason Cong and
                  Mau{-}Chung Frank Chang and
                  Glenn Reinman and
                  Sai{-}Wang Tam},
  editor       = {Chung{-}Kuan Cheng and
                  Sherief Reda},
  title        = {Multiband RF-interconnect for reconfigurable network-on-chip communications},
  booktitle    = {The 11th International Workshop on System-Level Interconnect Prediction
                  {(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
  pages        = {107--108},
  publisher    = {{ACM}},
  year         = {2009},
  url          = {https://doi.org/10.1145/1572471.1572491},
  doi          = {10.1145/1572471.1572491},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/slip/CongCRT09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/DingP09,
  author       = {Duo Ding and
                  David Z. Pan},
  editor       = {Chung{-}Kuan Cheng and
                  Sherief Reda},
  title        = {{OIL:} a nano-photonics optical interconnect library for a new photonic
                  networks-on-chip architecture},
  booktitle    = {The 11th International Workshop on System-Level Interconnect Prediction
                  {(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
  pages        = {11--18},
  publisher    = {{ACM}},
  year         = {2009},
  url          = {https://doi.org/10.1145/1572471.1572475},
  doi          = {10.1145/1572471.1572475},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/DingP09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/FathiBR09,
  author       = {Bahareh Fathi and
                  Laleh Behjat and
                  Logan M. Rakai},
  editor       = {Chung{-}Kuan Cheng and
                  Sherief Reda},
  title        = {A pre-placement net length estimation technique for mixed-size circuits},
  booktitle    = {The 11th International Workshop on System-Level Interconnect Prediction
                  {(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
  pages        = {45--52},
  publisher    = {{ACM}},
  year         = {2009},
  url          = {https://doi.org/10.1145/1572471.1572480},
  doi          = {10.1145/1572471.1572480},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/slip/FathiBR09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/FischbachLM09,
  author       = {Robert Fischbach and
                  Jens Lienig and
                  Tilo Meister},
  editor       = {Chung{-}Kuan Cheng and
                  Sherief Reda},
  title        = {From 3D circuit technologies and data structures to interconnect prediction},
  booktitle    = {The 11th International Workshop on System-Level Interconnect Prediction
                  {(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
  pages        = {77--84},
  publisher    = {{ACM}},
  year         = {2009},
  url          = {https://doi.org/10.1145/1572471.1572485},
  doi          = {10.1145/1572471.1572485},
  timestamp    = {Wed, 14 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/FischbachLM09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/HeDHG09,
  author       = {Xu He and
                  Sheqin Dong and
                  Xianlong Hong and
                  Satoshi Goto},
  editor       = {Chung{-}Kuan Cheng and
                  Sherief Reda},
  title        = {Integrated interlayer via planning and pin assignment for 3D ICs},
  booktitle    = {The 11th International Workshop on System-Level Interconnect Prediction
                  {(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
  pages        = {99--104},
  publisher    = {{ACM}},
  year         = {2009},
  url          = {https://doi.org/10.1145/1572471.1572488},
  doi          = {10.1145/1572471.1572488},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/HeDHG09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/HuZDZAPEC09,
  author       = {Xiang Hu and
                  Wenbo Zhao and
                  Peng Du and
                  Yulei Zhang and
                  Amirali Shayan Arani and
                  Christopher Pan and
                  A. Ege Engin and
                  Chung{-}Kuan Cheng},
  editor       = {Chung{-}Kuan Cheng and
                  Sherief Reda},
  title        = {On the bound of time-domain power supply noise based on frequency-domain
                  target impedance},
  booktitle    = {The 11th International Workshop on System-Level Interconnect Prediction
                  {(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
  pages        = {69--76},
  publisher    = {{ACM}},
  year         = {2009},
  url          = {https://doi.org/10.1145/1572471.1572483},
  doi          = {10.1145/1572471.1572483},
  timestamp    = {Thu, 07 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/slip/HuZDZAPEC09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/JeongKT09,
  author       = {Kwangok Jeong and
                  Andrew B. Kahng and
                  Rasit Onur Topaloglu},
  editor       = {Chung{-}Kuan Cheng and
                  Sherief Reda},
  title        = {Is overlay error more important than interconnect variations in double
                  patterning?},
  booktitle    = {The 11th International Workshop on System-Level Interconnect Prediction
                  {(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
  pages        = {3--10},
  publisher    = {{ACM}},
  year         = {2009},
  url          = {https://doi.org/10.1145/1572471.1572474},
  doi          = {10.1145/1572471.1572474},
  timestamp    = {Tue, 21 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/JeongKT09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/JevticCP09,
  author       = {Ruzica Jevtic and
                  Carlos Carreras and
                  Vukasin Pejovic},
  editor       = {Chung{-}Kuan Cheng and
                  Sherief Reda},
  title        = {Floorplan-based {FPGA} interconnect power estimation in {DSP} circuits},
  booktitle    = {The 11th International Workshop on System-Level Interconnect Prediction
                  {(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
  pages        = {53--60},
  publisher    = {{ACM}},
  year         = {2009},
  url          = {https://doi.org/10.1145/1572471.1572481},
  doi          = {10.1145/1572471.1572481},
  timestamp    = {Mon, 26 Jun 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/slip/JevticCP09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/KimML09,
  author       = {Dae Hyun Kim and
                  Saibal Mukhopadhyay and
                  Sung Kyu Lim},
  editor       = {Chung{-}Kuan Cheng and
                  Sherief Reda},
  title        = {Through-silicon-via aware interconnect prediction and optimization
                  for 3D stacked ICs},
  booktitle    = {The 11th International Workshop on System-Level Interconnect Prediction
                  {(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
  pages        = {85--92},
  publisher    = {{ACM}},
  year         = {2009},
  url          = {https://doi.org/10.1145/1572471.1572486},
  doi          = {10.1145/1572471.1572486},
  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/slip/KimML09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/Nayak09,
  author       = {Saroj K. Nayak},
  editor       = {Chung{-}Kuan Cheng and
                  Sherief Reda},
  title        = {Carbon nanotube, graphene and atomic wires as next generation interconnects:
                  current status and future promise},
  booktitle    = {The 11th International Workshop on System-Level Interconnect Prediction
                  {(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
  pages        = {109--110},
  publisher    = {{ACM}},
  year         = {2009},
  url          = {https://doi.org/10.1145/1572471.1572492},
  doi          = {10.1145/1572471.1572492},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/Nayak09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/Reda09,
  author       = {Sherief Reda},
  editor       = {Chung{-}Kuan Cheng and
                  Sherief Reda},
  title        = {Using circuit structural analysis techniques for networks in systems
                  biology},
  booktitle    = {The 11th International Workshop on System-Level Interconnect Prediction
                  {(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
  pages        = {37--44},
  publisher    = {{ACM}},
  year         = {2009},
  url          = {https://doi.org/10.1145/1572471.1572478},
  doi          = {10.1145/1572471.1572478},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/Reda09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/Saraswat09,
  author       = {Krishna Saraswat},
  editor       = {Chung{-}Kuan Cheng and
                  Sherief Reda},
  title        = {Performance comparison of cu/low-k, carbon nanotube, and optics for
                  on-chip and off-chip interconnects},
  booktitle    = {The 11th International Workshop on System-Level Interconnect Prediction
                  {(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
  pages        = {111--112},
  publisher    = {{ACM}},
  year         = {2009},
  url          = {https://doi.org/10.1145/1572471.1572493},
  doi          = {10.1145/1572471.1572493},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/Saraswat09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/SunL09,
  author       = {Peng Sun and
                  Rong Luo},
  editor       = {Chung{-}Kuan Cheng and
                  Sherief Reda},
  title        = {Closed-form solution for timing analysis of process variations on
                  {SWCNT} interconnect},
  booktitle    = {The 11th International Workshop on System-Level Interconnect Prediction
                  {(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
  pages        = {19--26},
  publisher    = {{ACM}},
  year         = {2009},
  url          = {https://doi.org/10.1145/1572471.1572476},
  doi          = {10.1145/1572471.1572476},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/SunL09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/ZhangHDEBC09,
  author       = {Yulei Zhang and
                  Xiang Hu and
                  Alina Deutsch and
                  A. Ege Engin and
                  James F. Buckwalter and
                  Chung{-}Kuan Cheng},
  editor       = {Chung{-}Kuan Cheng and
                  Sherief Reda},
  title        = {Prediction of high-performance on-chip global interconnection},
  booktitle    = {The 11th International Workshop on System-Level Interconnect Prediction
                  {(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
  pages        = {61--68},
  publisher    = {{ACM}},
  year         = {2009},
  url          = {https://doi.org/10.1145/1572471.1572482},
  doi          = {10.1145/1572471.1572482},
  timestamp    = {Thu, 10 Oct 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/slip/ZhangHDEBC09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/ZhangYHAEC09,
  author       = {Wanping Zhang and
                  Wenjian Yu and
                  Xiang Hu and
                  Amirali Shayan Arani and
                  A. Ege Engin and
                  Chung{-}Kuan Cheng},
  editor       = {Chung{-}Kuan Cheng and
                  Sherief Reda},
  title        = {Predicting the worst-case voltage violation in a 3D power network},
  booktitle    = {The 11th International Workshop on System-Level Interconnect Prediction
                  {(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
  pages        = {93--98},
  publisher    = {{ACM}},
  year         = {2009},
  url          = {https://doi.org/10.1145/1572471.1572487},
  doi          = {10.1145/1572471.1572487},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/ZhangYHAEC09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@proceedings{DBLP:conf/slip/2009,
  editor       = {Chung{-}Kuan Cheng and
                  Sherief Reda},
  title        = {The 11th International Workshop on System-Level Interconnect Prediction
                  {(SLIP} 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings},
  publisher    = {{ACM}},
  year         = {2009},
  isbn         = {978-1-60558-576-5},
  timestamp    = {Mon, 23 Nov 2009 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/2009.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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