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@inproceedings{DBLP:conf/vlsic/0002L0YKWP0SYKO18,
author = {Xiao Wu and
Inhee Lee and
Qing Dong and
Kaiyuan Yang and
Dongkwun Kim and
Jingcheng Wang and
Yimai Peng and
Yiqun Zhang and
Mehdi Saligane and
Makoto Yasuda and
Kazuyuki Kumeno and
Fumitaka Ohno and
Satoru Miyoshi and
Masaru Kawaminami and
Dennis Sylvester and
David T. Blaauw},
title = {A 0.04MM\({}^{\mbox{3}}\)16NW Wireless and Batteryless Sensor System
with Integrated Cortex-M0+ Processor and Optical Communication for
Cellular Temperature Measurement},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {191--192},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502391},
doi = {10.1109/VLSIC.2018.8502391},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/0002L0YKWP0SYKO18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/AielloCA18,
author = {Orazio Aiello and
Paolo Crovetti and
Massimo Alioto},
title = {A Sub-Leakage PW-Power HZ-Range Relaxation Oscillator Operating with
0.3V-1.8V Unregulated Supply},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {119--120},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502413},
doi = {10.1109/VLSIC.2018.8502413},
timestamp = {Mon, 16 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/AielloCA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/AkitaOKFA18,
author = {Ippei Akita and
Takayuki Okazawa and
Yoshihiko Kurui and
Akira Fujimoto and
Takashi Asano},
title = {A 181NW 970{\(\mathrm{\mu}\)}G{\unicode{10003}}HZ Accelerometer Analog
Front-End Employing Feedforward Noise Reduction Technique},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {161--162},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502314},
doi = {10.1109/VLSIC.2018.8502314},
timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/AkitaOKFA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/AndersKMSSAHK18,
author = {Mark A. Anders and
Himanshu Kaul and
Sanu Mathew and
Vikram B. Suresh and
Sudhir Satpathy and
Amit Agarwal and
Steven Hsu and
Ram Krishnamurthy},
title = {2.9TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator
with Unified {INT8/INTI6/FP16} Datapath in 14NM Tri-Gate {CMOS}},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {39--40},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502333},
doi = {10.1109/VLSIC.2018.8502333},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/AndersKMSSAHK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/BadamiMHV18,
author = {Komail M. H. Badami and
Kushal Dakshina Murthy and
Pieter Harpe and
Marian Verhelst},
title = {A 0.6V 54DB {SNR} Analog Frontend with 0.18{\%} {THD} for Low Power
Sensory Applications in 65NM {CMOS}},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {241--242},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502343},
doi = {10.1109/VLSIC.2018.8502343},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/BadamiMHV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/BaekLKMCHAKSKKK18,
author = {Jin{-}Hyeok Baek and
Chang{-}Kyo Lee and
Kiho Kim and
Daesik Moon and
Gil{-}Hoon Cha and
Jin{-}Seok Heo and
Min{-}Su Ahn and
Dong{-}Ju Kim and
Jae{-}Joon Song and
Seokhong Kwon and
Jongmin Kim and
Kyung{-}Soo Kim and
Jinoh Ahn and
Jeong{-}Sik Nam and
Byung{-}Cheol Kim and
Jeong{-}Hyeon Cho and
Jeonghoon Oh and
Seung{-}Jun Bae and
Indal Song and
Seok{-}Hun Hyun and
Ilgweon Kim and
Hyuck{-}Joon Kwon and
Young{-}Soo Sohn and
Jung{-}Hwan Choi and
Kwang{-}Il Park and
Seong{-}Jin Jang},
title = {A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up
Time Using 2-Step Charging Control and VOHCalibration in 20NM {DRAM}
Process},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {147--148},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502299},
doi = {10.1109/VLSIC.2018.8502299},
timestamp = {Fri, 25 Jan 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/BaekLKMCHAKSKKK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/BangJJC18,
author = {Jun{-}Suk Bang and
Hyuntak Jeon and
Minkyu Je and
Gyu{-}Hyeong Cho},
title = {6.5{\(\mathrm{\mu}\)}W 92.3DB-DR Biopotential-Recording Front-End
with 360MVPP Linear Input Range},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {239--240},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502264},
doi = {10.1109/VLSIC.2018.8502264},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/BangJJC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ButzenS18,
author = {Nicolas Butzen and
Michiel Steyaert},
title = {A Single-Topology Continuously-Scalable-Conversion-Ratio Fully Integrated
Switched-Capacitor {DC-DC} Converter with 0-to-2.22V Output and 93{\%}
Peak-Efficiency},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {103--104},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502308},
doi = {10.1109/VLSIC.2018.8502308},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ButzenS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/CaoSTSKYKATTK18,
author = {Chen Cao and
Yuya Shirakawa and
Leyi Tan and
Min{-}Woong Seo and
Keiichiro Kagawa and
Keita Yasutomi and
Tomohiko Kosugi and
Satoshi Aoyama and
Nobukazu Teranishi and
Norimichi Tsumura and
Shoji Kawahito},
title = {A Two-Tap {NIR} Lock-in Pixel {CMOS} Image Sensor with Background
Light Cancelling Capability for Non-Contact Heart Rate Detection},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {75--76},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502349},
doi = {10.1109/VLSIC.2018.8502349},
timestamp = {Mon, 16 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/CaoSTSKYKATTK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/CarimattoULDRPC18,
author = {Augusto Carimatto and
Arin C. Ulku and
Scott Lindner and
E. D'Aillon and
Bruce Rae and
Sara Pellegrini and
Edoardo Charbon},
title = {Multipurpose, Fully-Integrated 128{\texttimes}128 Event-Driven MD-SiPM
with 512 16-Bit TDCs with 45 {PS} {LSB} and 20 {NS} Gating},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {73--74},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502337},
doi = {10.1109/VLSIC.2018.8502337},
timestamp = {Thu, 28 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/CarimattoULDRPC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ChangNHA18,
author = {Eric Chang and
Nathan Narevsky and
Jaeduk Han and
Elad Alon},
title = {An Automated SerDes Frontend Generator Verified with a 16NM Instance
Achieving 15 {GB/S} at 1.96 PJ/Bit},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {153--154},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502313},
doi = {10.1109/VLSIC.2018.8502313},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/ChangNHA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ChenCLTTHH18,
author = {Mingyi Chen and
Ivan Dario Castro and
Qiuyang Lin and
Tom Torfs and
Filip Tavernier and
Chris Van Hoof and
Nick Van Helleputte},
title = {A 400G{\(\Omega\)} Input-Impedance, 220MVpp Linear-Input-Range, 2.8Vpp
CM-Interference-Tolerant Active Electrode for Non-Contact Capacitively
Coupled {ECG} Acquisition},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {129--130},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502270},
doi = {10.1109/VLSIC.2018.8502270},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ChenCLTTHH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ChenHCLLT18,
author = {Shao{-}Qi Chen and
Chia{-}Ming Huang and
Ke{-}Horng Chen and
Ying{-}Hsi Lin and
Shian{-}Ru Lin and
Tsung{-}Yen Tsai},
title = {An Ultra-low Quiescent Current 250NA Low Dropout Regulator for No-Load
to 10MA Internet-of-Evervthing Applications},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {229--230},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502414},
doi = {10.1109/VLSIC.2018.8502414},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/ChenHCLLT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ChenKSKK18,
author = {Gregory K. Chen and
Raghavan Kumar and
Huseyin Ekin Sumbul and
Phil C. Knag and
Ram K. Krishnamurthy},
title = {A 4096-Neuron 1M-Synapse 3.8PJ/SOP Spiking Neural Network with On-Chip
{STDP} Learning and Sparse Weights in 10NM FinFET {CMOS}},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {255--256},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502423},
doi = {10.1109/VLSIC.2018.8502423},
timestamp = {Mon, 30 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ChenKSKK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ChenZYZL18,
author = {Haiwen Chen and
Xiong Zhot and
Qiang Yu and
Fan Zhang and
Qiang Li},
title = {A {\textgreater}3GHz {ERBW} 1.1GS/S 8B Two-Sten {SAR} {ADC} with Recursive-Weight
{DAC}},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {97--98},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502370},
doi = {10.1109/VLSIC.2018.8502370},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/ChenZYZL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ChiuCAPN18,
author = {Pi{-}Feng Chiu and
Christopher Celio and
Krste Asanovic and
David A. Patterson and
Borivoje Nikolic},
title = {An Out-of-Order {RISC-V} Processor with Resilient Low-Voltage Operation
in 28NM {CMOS}},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {61--62},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502320},
doi = {10.1109/VLSIC.2018.8502320},
timestamp = {Thu, 13 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ChiuCAPN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/Choi0KPS18,
author = {Woong Choi and
Jongsun Park and
Hoonki Kim and
Changnam Park and
Taejoong Song},
title = {Half-and-Half Compare Content Addressable Memory with Charge-Sharing
Based Selective Match-Line Precharge Scheme},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {17--18},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502311},
doi = {10.1109/VLSIC.2018.8502311},
timestamp = {Fri, 27 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/Choi0KPS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ChoiHPYBSJYYAKH18,
author = {Sung{-}Won Choi and
Yeunhee Huh and
Sang{-}Hui Park and
Kye{-}Seok Yoon and
Jun{-}Suk Bang and
Se{-}Un Shin and
Yong{-}Min Ju and
Yu{-}Jin Yang and
Junghyuk Yoon and
Changyong Ahn and
Taekseung Kim and
Sung{-}Wan Hong and
Gyu{-}Hyeong Cho},
title = {A Quasi-Digital Ultra-Fast Capacitor-Less Low-Dropout Regulator Based
on Comparator Control for x8 Current Spike of {PCRAM} Systems},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {107--108},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502348},
doi = {10.1109/VLSIC.2018.8502348},
timestamp = {Wed, 31 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/ChoiHPYBSJYYAKH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ChoiYLJLLC18,
author = {Seojin Choi and
Seyeon Yoo and
Yongsun Lee and
Yongwoo Jo and
Jeonghyun Lee and
Younghyun Lim and
Jaehyouk Choi},
title = {153 FSRMS-Integrated-Jitter and 114-Multiplication Factor PVT-Robust
22.8 {GHZ} Ring-LC-Hybrid Injection-Locked Clock Multiplier},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {185--186},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502355},
doi = {10.1109/VLSIC.2018.8502355},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/ChoiYLJLLC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/DallyGPK0D18,
author = {William J. Dally and
C. Thomas Gray and
John Poulton and
Brucek Khailany and
John M. Wilson and
Larry R. Dennison},
title = {Hardware-Enabled Artificial Intelligence},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {3--6},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502368},
doi = {10.1109/VLSIC.2018.8502368},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/DallyGPK0D18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/DingZL18,
author = {Zhaoming Ding and
Xiong Zhou and
Qiang Li},
title = {A 0.5-1.1V 10B Adaptive Bypassing {SAR} {ADC} Utilizing Oscillation
Cycle Information of VCO-Based Comparator},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {93--94},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502440},
doi = {10.1109/VLSIC.2018.8502440},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/DingZL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ErdmannVVPMKTOL18,
author = {Christophe Erdmann and
Bob Verbruggen and
Bruno Vaz and
Roberto Pelliconi and
John McGrath and
Ryan Kinnerk and
Ronnie De La Torre and
John O'Dwyer and
Patrick Lynch and
Padraig Kelly and
Peng Lim and
Daire Breathnach and
Brendan Farley},
title = {A modular 16NM Direct-RF {TX/RX} Embedding 9GS/S {DAC} and 4.5GS/S
{ADC} with 90DB Isolation and Sub-80PS Channel Alignment for Monolithic
Integration in 5G Base-Station SoC},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {219--220},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502292},
doi = {10.1109/VLSIC.2018.8502292},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/ErdmannVVPMKTOL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/FleischerSZSOSC18,
author = {Bruce M. Fleischer and
Sunil Shukla and
Matthew M. Ziegler and
Joel Silberman and
Jinwook Oh and
Vijayalakshmi Srinivasan and
Jungwook Choi and
Silvia M. Mueller and
Ankur Agrawal and
Tina Babinsky and
Nianzheng Cao and
Chia{-}Yu Chen and
Pierce Chuang and
Thomas W. Fox and
George Gristede and
Michael Guillorn and
Howard Haynie and
Michael J. Klaiber and
Dongsoo Lee and
Shih{-}Hsien Lo and
Gary W. Maier and
Michael Scheuermann and
Swagath Venkataramani and
Christos Vezyrtzis and
Naigang Wang and
Fanchieh Yee and
Ching Zhou and
Pong{-}Fei Lu and
Brian W. Curran and
Leland Chang and
Kailash Gopalakrishnan},
title = {A Scalable Multi- TeraOPS Deep Learning Processor Core for {AI} Trainina
and Inference},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {35--36},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502276},
doi = {10.1109/VLSIC.2018.8502276},
timestamp = {Tue, 22 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/FleischerSZSOSC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/FranceseCOBMMKK18,
author = {Pier Andrea Francese and
Alessandro Cevrero and
Ilter {\"{O}}zkaya and
Matthias Br{\"{a}}ndli and
Christian Menolfi and
Thomas Morf and
Marcel A. Kossel and
Lukas Kull and
Danny Luu and
Thomas Toifl},
title = {A 50GB/S 1.6PJ/B {RX} Data-Path with Quarter-Rate 3-Tap Speculative
{DFE}},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {267--268},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502359},
doi = {10.1109/VLSIC.2018.8502359},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/FranceseCOBMMKK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/FujiiTTTKNNNM18,
author = {Taro Fujii and
Takao Toi and
Teruhito Tanaka and
Katsumi Togawa and
Toshiro Kitaoka and
Kengo Nishino and
Noritsugu Nakamura and
Hiroki Nakahara and
Masato Motomura},
title = {New Generation Dynamically Reconfigurable Processor Technology for
Accelerating Embedded {AI} Applications},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {41--42},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502438},
doi = {10.1109/VLSIC.2018.8502438},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/FujiiTTTKNNNM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/GarelloYCSSRBKL18,
author = {Kevin Garello and
Kevin Garello Yasin and
S. Couet and
Laurent Souriau and
Johan Swerts and
Sidharth Rao and
Simon Van Beek and
Wonsub Kim and
Enlong Liu and
Shreya Kundu and
Diana Tsvetanova and
Kris Croes and
N. Jossart and
E. Grimaldi and
M. Baumgartner and
D. Crotti and
Arnaud Fumemont and
Pietro Gambardella and
Gouri Sankar Kar},
title = {{SOT-MRAM} 300MM Integration for Low Power and Ultrafast Embedded
Memories},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {81--82},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502269},
doi = {10.1109/VLSIC.2018.8502269},
timestamp = {Wed, 07 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/GarelloYCSSRBKL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/GeorgeSJL18,
author = {Arup K. George and
Wooyoon Shim and
Minkyu Je and
Junghyup Lee},
title = {A 114-AF {RMS-} Resolution 46-NF/10-M{\(\Omega\)} -Range Digital-Intensive
Reconfigurable RC-to-Digital Converter with Parasitic-Insensitive
Femto-Farad Baseline Sensing},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {157--158},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502332},
doi = {10.1109/VLSIC.2018.8502332},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/GeorgeSJL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/HuangCLY18,
author = {Shuo{-}An Huang and
Kai{-}Chieh Chang and
Horng{-}Huei Liou and
Chia{-}Hsiang Yang},
title = {A 1.9MW {SVM} Processor with On-Chip Active Learning for Epileptic
Seizure Control},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {259--260},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502428},
doi = {10.1109/VLSIC.2018.8502428},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/HuangCLY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/HudnerCCHNCEPLZ18,
author = {James Hudner and
Declan Carey and
Ronan Casey and
Kay Hearne and
Pedro Wilson de Abreu Farias Neto and
Ilias Chlis and
Marc Erett and
Chi Fung Poon and
Asma Laraba and
Hongtao Zhang and
Sai Lalith Chaitanya Ambatipudi and
David Mahashin and
Parag Upadhyaya and
Yohan Frans and
Ken Chang},
title = {A 112GB/S {PAM4} Wireline Receiver Using a 64-Way Time-Interleaved
{SAR} {ADC} in 16NM FinFET},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {47--48},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502436},
doi = {10.1109/VLSIC.2018.8502436},
timestamp = {Thu, 30 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/HudnerCCHNCEPLZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/HuhSHWJCC18,
author = {Yeunhee Huh and
Se{-}Un Shin and
Sung{-}Wan Hong and
Young{-}Jin Woo and
Yong{-}Min Ju and
Sung{-}Won Choi and
Gyu{-}Hyeong Cho},
title = {A Hybrid Dual-Path Step-Down Converter with 96.2{\%} Peak Efficiency
Using a {\textdollar}250{\textbackslash}text\{m\}{\textdollar} {\(\mu\)}
Large-DCR Inductor},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {225--226},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502284},
doi = {10.1109/VLSIC.2018.8502284},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/HuhSHWJCC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/Hunt-SchroederA18,
author = {Eric Hunt{-}Schroeder and
Darren Anand and
John A. Fifield and
Mark Jacunski and
Michael Roberge and
Dale E. Pontius and
Kevin Batson and
Toshiaki Kirihata},
title = {14NM FinFET 1.5MB Embedded High-K Charge Trap Transistor One Time
Programmable Memory Using Dynamic Adaptive Programming},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {87--88},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502415},
doi = {10.1109/VLSIC.2018.8502415},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/Hunt-SchroederA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/IbrahimFKEH18,
author = {Mohamed I. Ibrahim and
Christopher Foy and
Donggyu Kim and
Dirk R. Englund and
Ruonan Han},
title = {Room-Temperature Quantum Sensing in {CMOS:} On-Chip Detection of Electronic
Spin States in Diamond Color Centers for Magnetometry},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {249--250},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502329},
doi = {10.1109/VLSIC.2018.8502329},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/IbrahimFKEH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ImCFCZZCMLCZTBT18,
author = {Jay Im and
Stanley Chen and
Dave Freitas and
Adam Chou and
Lei Zhou and
Ian Zhuang and
Tim Cronin and
David Mahashin and
Winson Lin and
Kok Lim Chan and
Hongyuan Zhao and
Kee Hian Tan and
Ade Bekele and
Didem Turker and
Parag Upadhyaya and
Yohan Frans and
Ken Chang},
title = {A 0.5-28GB/S Wireline Tranceiver with 15-Tap {DFE} and Fast-Locking
Digital {CDR} in 7NM FinFET},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {145--146},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502275},
doi = {10.1109/VLSIC.2018.8502275},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ImCFCZZCMLCZTBT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/IntiMKVHMJC18,
author = {Rajesh Inti and
Mozhgan Mansuri and
Joe Kennedy and
Hariprasath Venkatram and
Chun{-}Ming Hsu and
Aaron Martin and
James E. Jaussi and
Bryan Casper},
title = {A Digital-Intensive 2-to-9.2 GB/S/Pin Memory Controller {I/O} with
Fast-Response {LDO} in 10NM {CMOS}},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {151--152},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502323},
doi = {10.1109/VLSIC.2018.8502323},
timestamp = {Wed, 02 Mar 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/IntiMKVHMJC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/JangLCNLOJCSB18,
author = {Tae{-}Kwang Jang and
Jongyup Lim and
Kyojin David Choo and
Samuel Nason and
Jeongsup Lee and
Jeongsup Oh and
Seokhyeon Jeong and
Cynthia A. Chestek and
Dennis Sylvester and
David T. Blaauw},
title = {A 2.2 {NEF} Neural-Recording Amplifier Using Discrete-Time Parametric
Amplification},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {237--238},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502432},
doi = {10.1109/VLSIC.2018.8502432},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/JangLCNLOJCSB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/JelokaWXKBSB18,
author = {Supreet Jeloka and
Zhehong Wang and
Ruochen Xie and
Sudhanshu Khanna and
Steven Bartling and
Dennis Sylvester and
David T. Blaauw},
title = {Energy Efficient Adiabatic {FRAM} with 0.99 PJ/Bit Write for IoT Applications},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {85--86},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502265},
doi = {10.1109/VLSIC.2018.8502265},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/JelokaWXKBSB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/JiangAVSN18,
author = {Hui Jiang and
Samira Amani and
Johan G. Vogel and
Saleh Heidary Shalmany and
Stoyan N. Nihtianov},
title = {A 117DB in-Band {CMRR} 98.5DB {SNR} Capacitance-to-Digital Converter
for Sub-NM Displacement Sensing with an Electrically Floating Target},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {159--160},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502363},
doi = {10.1109/VLSIC.2018.8502363},
timestamp = {Fri, 08 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/JiangAVSN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/JuCJJ18,
author = {Haram Ju and
Moon{-}Chul Choi and
Gyu{-}Seob Jeong and
Deog{-}Kyoon Jeong},
title = {A 64 GB/s 1.5 PJ/Bit {PAM-4} Transmitter with 3-Tap {FFE} and GM-Regulated
Active-Feedback Driver in 28 {NM} {CMOS}},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {51--52},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502380},
doi = {10.1109/VLSIC.2018.8502380},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/JuCJJ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/KakushimaHWSFST18,
author = {Kuniyuki Kakushima and
Takuya Hoshii and
M. Watanabe and
N. Shizyo and
K. Furukawa and
Takuya Saraya and
T. Takakura and
K. Itou and
M. Fukui and
S. Suzuki and
Ken Takeuchi and
Iriya Muneta and
Hitoshi Wakabayashi and
Y. Numasawa and
Atsushi Ogura and
Shinichi Nishizawa and
Kazuo Tsutsui and
Toshiro Hiramoto and
H. Ohashi and
Hiroshi Iwai},
title = {New Methodology for Evaluating Minority Carrier Lifetime for Process
Assessment},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {105--106},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502399},
doi = {10.1109/VLSIC.2018.8502399},
timestamp = {Thu, 17 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/KakushimaHWSFST18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/KangLKY18,
author = {Sanghoon Kang and
Jinmook Lee and
Changhyeon Kim and
Hoi{-}Jun Yoo},
title = {B-Face: 0.2 {MW} CNN-Based Face Recognition Processor with Face Alignment
for Mobile User Identification},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {137--138},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502266},
doi = {10.1109/VLSIC.2018.8502266},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/KangLKY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/KarasawaFM18,
author = {Yuki Karasawa and
Takanobu Fukuoka and
Kousuke Miyaji},
title = {A 92.8{\%} Efficiency Adaptive-On/Off-Time Control 3-Level Buck Converter
for Wide Conversion Ratio with Shared Charge Pump Intermediate Voltage
Regulator},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {227--228},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502403},
doi = {10.1109/VLSIC.2018.8502403},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/KarasawaFM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/KatayamaMSH18,
author = {Takato Katayama and
Shiko Miyashita and
Kazuki Sobue and
Koichi Hamashita},
title = {A 1.25MS/S Two-Step Incremental {ADC} with 100DB {DR} and 110DB {SFDR}},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {205--206},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502298},
doi = {10.1109/VLSIC.2018.8502298},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/KatayamaMSH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/KimKSHK18,
author = {Doyun Kim and
Sung Kim and
Mingoo Seok and
Hyunju Ham and
Jongwhan Kim},
title = {0.5V-VIN, 165-MA/MM\({}^{\mbox{2}}\) Fully-Integrated Digital {LDO}
Based on Event-Driven Self-Trisuerina Control},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {109--110},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502272},
doi = {10.1109/VLSIC.2018.8502272},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/KimKSHK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/KimVSLKWLKKRTD18,
author = {Suhwan Kim and
Vaibhav A. Vaidya and
Christopher Schaef and
Andrew Lines and
Harish Krishnamurthy and
Sheldon Weng and
Xiaosen Liu and
Dileep Kurian and
Tanay Karnik and
Krishnan Ravichandran and
James W. Tschanz and
Vivek De},
title = {A Single-Stage, Single-Inductor, 6-Input 9-Output Multi-Modal Energy
Harvesting Power Management {IC} for 100{\(\mathrm{\mu}\)}W-120MW
Battery-Powered IoT Edge Nodes},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {195--196},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502301},
doi = {10.1109/VLSIC.2018.8502301},
timestamp = {Wed, 01 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/KimVSLKWLKKRTD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/KomatsuzakiMHKK18,
author = {Tsuneo Komatsuzaki and
Yasushi Matsumoto and
Yoshihiko Hiraoka and
Yohei Kaieda and
Hiroki Kunii},
title = {Semiconductor Technologies Accelerate Our Future Vision: "ANSHIN Platform"},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {1--4},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502360},
doi = {10.1109/VLSIC.2018.8502360},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/KomatsuzakiMHKK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/KongCR18,
author = {Long Kong and
Yikun Chang and
Behzad Razavi},
title = {A 14 {\(\mathrm{\mu}\)}M {\texttimes} 26 {\(\mathrm{\mu}\)}M 20-GB/S
3-MW {CDR} Circuit with High Jitter Tolerance},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {271--272},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502278},
doi = {10.1109/VLSIC.2018.8502278},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/KongCR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/KoyamaISTNISSUK18,
author = {Shinzo Koyama and
Motonori Ishii and
Shigeru Saito and
Masato Takemoto and
Yugo Nose and
Akito Inoue and
Yusuke Sakata and
Yuki Sugiura and
Manabu Usuda and
Tatsuya Kabe and
Shigetaka Kasuga and
Mitsuyoshi Mori and
Yutaka Hirose and
Akihiro Odagawa and
Tsuyoshi Tanaka},
title = {A 220 M-Range Direct Time-of-Flight 688 {\texttimes} 384 {CMOS} Image
Sensor with Sub-Photon Signal Extraction {(SPSE)} Pixels Using Vertical
Avalanche Photo-Diodes and 6 KHz Light Pulse Counters},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {71--72},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502408},
doi = {10.1109/VLSIC.2018.8502408},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/KoyamaISTNISSUK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/KuanWSCHC18,
author = {Ting{-}Kuei Kuan and
Chin{-}Yang Wu and
Ruei{-}Pin Shen and
Chih{-}Hsien Chang and
Kenny Hsieh and
Mark Chen},
title = {A Digital Bang-Bang Phase-Locked Loop with Background Injection Timing
Calibration and Automatic Loop Gain Control in 7NM FinFET {CMOS}},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {179--180},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502365},
doi = {10.1109/VLSIC.2018.8502365},
timestamp = {Fri, 16 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/KuanWSCHC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/KullLMMFBKCOT18,
author = {Lukas Kull and
Danny Luu and
Christian Menolfi and
Thomas Morf and
Pier Andrea Francese and
Matthias Braendli and
Marcel A. Kossel and
Alessandro Cevrero and
Ilter {\"{O}}zkaya and
Thomas Toifl},
title = {A 10-Bit 20-40 {GS/S} {ADC} with 37 dB {SNDR} at 40 GHz Input Using
First Order Sampling Bandwidth Calibration},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {275--276},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502268},
doi = {10.1109/VLSIC.2018.8502268},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/KullLMMFBKCOT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/LeeJC18,
author = {Changwook Lee and
Moon Hyung Jang and
Youngcheol Chae},
title = {A 1.2V 68{\(\mathrm{\mu}\)}W 98.2DB-DR Audio Continuous-Time Delta-Sigma
Modulator},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {199--200},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502318},
doi = {10.1109/VLSIC.2018.8502318},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/LeeJC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/LeeKMJKPB18,
author = {Inhee Lee and
Gyouho Kim and
Eunseong Moon and
Seokhyeon Jeong and
Dongkwun Kim and
Jamie Phillips and
David T. Blaauw},
title = {A 179-Lux Energy-Autonomous Fully-Encapsulated 17-mm\({}^{\mbox{3}}\)
Sensor Node with Initial Charge Delay Circuit for Battery Protection},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {251--252},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502287},
doi = {10.1109/VLSIC.2018.8502287},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/LeeKMJKPB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/LeeLHKLY18,
author = {Jaehyuk Lee and
Kyoung{-}Rog Lee and
Unsoo Ha and
Ji{-}Hoon Kim and
Kwonjoon Lee and
Hoi{-}Jun Yoo},
title = {A 0.8V 82.9{\(\mathrm{\mu}\)}W In-Ear {BCI} Controller System with
8.8 {PEF} {EEG} Instrumentational Amplifier and Wireless {BAN} Transceiver},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {123--124},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502263},
doi = {10.1109/VLSIC.2018.8502263},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/LeeLHKLY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/LeeM18,
author = {Dhon{-}Gue Lee and
Patrick P. Mercier},
title = {{AMASS} {PLL:} An Active-Mixer-Adopted Sub-Sampling {PLL} Achieving
an {FOM} of -255.5DB and a Reference Spur of -66.6DBC},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {181--182},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502425},
doi = {10.1109/VLSIC.2018.8502425},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/LeeM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/LiWSBK18,
author = {Ziyun Li and
Jingcheng Wang and
Dennis Sylvester and
David T. Blaauw and
Hun{-}Seok Kim},
title = {{A1920} {\texttimes} 1080 25FPS, 2.4TOPS/W Unified Optical Flow and
Depth 6D Vision Processor for Energy-Efficient, Low Power Autonomous
Navigation},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {135--136},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502347},
doi = {10.1109/VLSIC.2018.8502347},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/LiWSBK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/LimJSYMKBS18,
author = {Jongyup Lim and
Tae{-}Kwang Jang and
Mehdi Saligane and
Makoto Yasuda and
Satoru Miyoshi and
Masaru Kawaminami and
David T. Blaauw and
Dennis Sylvester},
title = {A 224 {PW} 260 PPM/{\textdegree}C Gate-Leakage-Based Timer for Ultra-Low
Power Sensor Nodes with Second-Order Temperature Dependency Cancellation},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {117--118},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502374},
doi = {10.1109/VLSIC.2018.8502374},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/LimJSYMKBS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/LinMS18,
author = {Sen Lin and
Sajjad Moazeni and
Vladimir Stojanovic},
title = {A 40GB/S Optical {NRZ} Transmitter Based on Monolithic Microring Modulators
in 45NM {SOI} {CMOS}},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {273--274},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502396},
doi = {10.1109/VLSIC.2018.8502396},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/LinMS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/LindnerZAWC18,
author = {Scott Lindner and
Chao Zhang and
Ivan Michel Antolovic and
Martin Wolf and
Edoardo Charbon},
title = {A 252 {\texttimes} 144 {SPAD} Pixel Flash Lidar with 1728 Dual-Clock
48.8 {PS} TDCs, Integrated Histogramming and 14.9-to-1 Compression
in 180NM {CMOS} Technology},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {69--70},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502386},
doi = {10.1109/VLSIC.2018.8502386},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/LindnerZAWC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/LiuLGWS18,
author = {Jiaxin Liu and
Shaolan Li and
Wenjuan Guo and
Guangjun Wen and
Nan Sun},
title = {A 0.029MM2 17-FJ/Conv.-Step {CT} {\textdollar}{\textbackslash}Delta{\textbackslash}Sigma{\textdollar}
{ADC} with 2\({}^{\mbox{nd}}\)-Order Noise-Shaping {SAR} Quantizer},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {201--202},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502424},
doi = {10.1109/VLSIC.2018.8502424},
timestamp = {Mon, 25 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/LiuLGWS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/LiuTWLCCJ18,
author = {Tsu{-}Ming Liu and
Chang{-}Hung Tsai and
Tung{-}Hsing Wu and
Jia{-}Ying Lin and
Li{-}Heng Chen and
Han{-}Liang Chou and
Chi{-}Cheng Ju},
title = {A 0.76MM\({}^{\mbox{2}}\) 0.22NJ/Pixel DL-Assisted 4K Video Encoder
{LSI} for Quality-of-Experience Over Smart-Phones},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {257--258},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502304},
doi = {10.1109/VLSIC.2018.8502304},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/LiuTWLCCJ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/LuLYWH18,
author = {Danzhu Lu and
Peng Liu and
Suyi Yao and
Langyuan Wang and
Jie He},
title = {A 95.3{\%} Peak Efficiency, 135NA Quiescent Current Buck-Boost {DC-DC}
Converter with Current-Slope-Based Mode Control},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {223--224},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502407},
doi = {10.1109/VLSIC.2018.8502407},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/LuLYWH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/LuoH18,
author = {Yuxuan Luo and
Chun{-}Huat Heng},
title = {An 8.2 {\(\mathrm{\mu}\)}W 0.14 MM\({}^{\mbox{2}}\)16-Channel CDMA-Like
Period Modulation Capacitance-Tu-Diaital Converter with Reduced Data
Throuahput},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {165--166},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502217},
doi = {10.1109/VLSIC.2018.8502217},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/LuoH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/MaedaNKKNF18,
author = {Koji Maeda and
Takayasu Norimatsu and
Kenji Kogo and
Naohiro Kohmu and
Kei Nishimura and
Izumi Fukasaku},
title = {An Active Copper-Cable Supporting 56-Gbit/s {PAM4} and 28-Gbit/s {NRZ}
with Continuous Time Linear Equalizer {IC} for to-Meters Reach Interconnection},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {49--50},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502352},
doi = {10.1109/VLSIC.2018.8502352},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/MaedaNKKNF18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/MarkulicRMLWC18,
author = {Nereo Markulic and
Pratap Renukaswarny and
Ewout Martens and
Barend van Liempd and
Piet Wambacq and
Jan Craninckx},
title = {A 5.5 GHz Background-Calibrated Subsampling Polar Transmitter with
-41.3 {DB} {EVM} at 1024 {OAM} in 28NM {CMOS}},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {215--216},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502326},
doi = {10.1109/VLSIC.2018.8502326},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/MarkulicRMLWC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/MehtaHS18,
author = {Nandish Mehta and
Johan H. Huijsing and
Vladimir Stojanovic},
title = {A 1MW -101DB {THD+N} Class-AB High-Fidelity Headphone Driver in 65NM
{CMOS}},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {235--236},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502397},
doi = {10.1109/VLSIC.2018.8502397},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/MehtaHS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/MendrelaPVFY18,
author = {Adam E. Mendrela and
Sung{-}Yun Park and
Mih{\'{a}}ly V{\"{o}}r{\"{o}}slakos and
Michael P. Flynn and
Euisik Yoon},
title = {A Battery-Powered Opto-Electrophysiology Neural Interface with Artifact-Preventing
Optical Pulse Shaping},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {125--126},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502353},
doi = {10.1109/VLSIC.2018.8502353},
timestamp = {Wed, 12 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/MendrelaPVFY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/MengWKY18,
author = {Xiangyu Meng and
Can Wang and
Milad Kalantari and
C. Patrick Yue},
title = {A 16-GB/S 0-DB Power Back-Off 16-QAM Transmitter at 28 {GHZ} in 65-NM
{CMOS}},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {217--218},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502422},
doi = {10.1109/VLSIC.2018.8502422},
timestamp = {Fri, 29 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/MengWKY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/MilletCABGDBDDB18,
author = {Laurent Millet and
St{\'{e}}phane Chevobbe and
Caaliph Andriamisaina and
Edith Beign{\'{e}} and
Fabrice Guellec and
Thomas Dombek and
Lamine Benaissa and
Edouard Deschaseaux and
Marc Duranton and
K. Benchehida and
Mehdi Darouich and
Maria Lepecq},
title = {A 5500FPS 85GOPS/W 3D Stacked {BSI} Vision Chip Based on Parallel
in-Focal-Plane Acquisition and Processing},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {245--246},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502290},
doi = {10.1109/VLSIC.2018.8502290},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/MilletCABGDBDDB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/MiyaharaEOM18,
author = {Masaya Miyahara and
Yukiya Endo and
Kenichi Okada and
Akira Matsuzawa},
title = {A 64{\(\mu\)}s Start-Up 26/40MHz Crystal Oscillator with Negative
Resistance Boosting Technique Using Reconfigurable Multi-Stage Amplifier},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {115--116},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502281},
doi = {10.1109/VLSIC.2018.8502281},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/MiyaharaEOM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/NguyenJAJPYAANB18,
author = {Hoan Nguyen and
Jihoon Jeong and
Francois Atallah and
Marc Jansen and
Anthony Polomik and
Daniel Yingling and
Harsha Akkaraju and
Brad Appel and
Rahul Nadkarni and
Keith A. Bowman},
title = {A 7NM Double-Pumped 6R6W Register File for Machine Learning Memory},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {1--2},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502393},
doi = {10.1109/VLSIC.2018.8502393},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/NguyenJAJPYAANB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/Ohhata18,
author = {Kenichi Ohhata},
title = {A 2.3-MW, 950-MHz, 8-Bit Fully-Time-Based Subranging {ADC} Using Highly-Linear
Dynamic {VTC}},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {95--96},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502316},
doi = {10.1109/VLSIC.2018.8502316},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/Ohhata18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/PamulaSKRZS18,
author = {Rajesh Pamula and
Xun Sun and
Sung Kim and
Fahim ur Rahman and
Baosen Zhang and
Visvesh S. Sathe},
title = {An All-Digital True-Random-Number Generator with Integrated De-correlation
and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM {CMOS}},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {1--2},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502375},
doi = {10.1109/VLSIC.2018.8502375},
timestamp = {Wed, 30 Oct 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/PamulaSKRZS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/PanAJRM18,
author = {Jiacheng Pan and
Asad A. Abidi and
Wenlong Jiang and
Dejan Rozgic and
Dejan Markovic},
title = {Self-Regulated Wireless Power and Simultaneous 5MB/S Reverse Data
over One Pair of Coils},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {193--194},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502354},
doi = {10.1109/VLSIC.2018.8502354},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/PanAJRM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ParkJ18,
author = {Jun{-}Eun Park and
Deog{-}Kyoon Jeong},
title = {A Fully Integrated 700MA Event-Driven Digital Low-Dropout Regulator
with Residue-Tracking Loop for Fine-Grained Power Management Unit},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {231--232},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502295},
doi = {10.1109/VLSIC.2018.8502295},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ParkJ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ParkLC18,
author = {Sujin Park and
Geon{-}Hwi Lee and
SeongHwan Cho},
title = {A 2.69UW Dual Quantization-Based Capacitance-to-Digital Converter
for Pressure, Humidity, and Acceleration Sensing in 0.18UM {CMOS}},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {163--164},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502339},
doi = {10.1109/VLSIC.2018.8502339},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/ParkLC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/PazhouhandehKSW18,
author = {Mohammad Reza Pazhouhandeh and
Hossein Kassiri and
Aly Shoukry and
Iliya Weisspapir and
Peter L. Carlen and
Roman Genov},
title = {Artifact-Tolerant Opamp-Less Delta-Modulated Bidirectional Neuro-Interface},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {127--128},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502286},
doi = {10.1109/VLSIC.2018.8502286},
timestamp = {Tue, 12 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/PazhouhandehKSW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/RahmanKJKLPBS18,
author = {Fahim ur Rahman and
Sung Kim and
Naveen John and
Roshan Kumar and
Xi Li and
Rajesh Pamula and
Keith A. Bowman and
Visvesh S. Sathe},
title = {An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage
Regulator for Variation Tolerance in a Sub-Threshold {ARM} Cortex
{M0} Processor},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {65--66},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502303},
doi = {10.1109/VLSIC.2018.8502303},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/RahmanKJKLPBS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/SaliganeL0YKOMK18,
author = {Mehdi Saligane and
Jeongsup Lee and
Qing Dong and
Makoto Yasuda and
Kazuyuki Kumeno and
Fumitaka Ohno and
Satoru Miyoshi and
Masaru Kawaminami and
David T. Blaauw and
Dennis Sylvester},
title = {An Adaptive Body-Biaslna SoC Using in Situ Slack Monitoring for Runtime
Replica Calibration},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {63--64},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502411},
doi = {10.1109/VLSIC.2018.8502411},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/SaliganeL0YKOMK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/SatpathyMSAKAHK18,
author = {Sudhir Satpathy and
Sanu Mathew and
Vikram B. Suresh and
Mark A. Anders and
Himanshu Kaul and
Amit Agarwal and
Steven Hsu and
Ram Krishnamurthy and
Vivek De},
title = {An All-Digital Unified Static/Dynamic Entropy Generator Featuring
Self-Calibrating Hierarchical Von Neumann Extraction for Secure Privacy-Preserving
Mutual Authentication in IoT Mote Platforms},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {169--170},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502369},
doi = {10.1109/VLSIC.2018.8502369},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/SatpathyMSAKAHK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/SatpathySMAKAHK18,
author = {Sudhir Satpathy and
Vikram B. Suresh and
Sanu Mathew and
Mark A. Anders and
Himanshu Kaul and
Amit Agarwal and
Steven Hsu and
Ram Krishnamurthy},
title = {220MV-900MV 794/584/754 {GBPS/W} Reconfigurable GF(2\({}^{\mbox{4}}\))2
AES/SMS4/Camellia Symmetric-Key Cipher Accelerator in 14NM Tri-Gate
{CMOS}},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {175--176},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502262},
doi = {10.1109/VLSIC.2018.8502262},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/SatpathySMAKAHK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/SawabyWSCNKA18,
author = {Ahmed Sawaby and
Max L. Wang and
Ernest So and
Jun{-}Chau Chien and
Hao Nan and
Butrus T. Khuri{-}Yakub and
Amin Arbabian},
title = {A Wireless Implantable Ultrasound Array Receiver for Thermoacoustic
Imaging},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {189--190},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502293},
doi = {10.1109/VLSIC.2018.8502293},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/SawabyWSCNKA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ShenSLC18,
author = {Junhua Shen and
Akira Shikata and
Anping Liu and
Frederick Chalifoux},
title = {A 12-Bit 31.1UW 1MS/S {SAR} {ADC} with On-Chip Input-Signal-Independent
Calibration Achieving 100.4DB {SFDR} Using 256FF Sampling Capacitance},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {91--92},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502325},
doi = {10.1109/VLSIC.2018.8502325},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/ShenSLC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ShihLCLLCLYYCCC18,
author = {Yi{-}Chun Shih and
Chia{-}Fu Lee and
Yen{-}An Chang and
Po{-}Hao Lee and
Hon{-}Jarn Lin and
Yu{-}Lin Chen and
Ku{-}Feng Lin and
Ta{-}Ching Yeh and
Hung{-}Chang Yu and
Harry Chuang and
Yu{-}Der Chih and
Tsung{-}Yung Jonathan Chang},
title = {Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with
Hybrid-Resistance Reference, Sub-{\(\mu\)}A Sensing Resolution, and
17.5NS Read Access Time},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {79--80},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502260},
doi = {10.1109/VLSIC.2018.8502260},
timestamp = {Wed, 07 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ShihLCLLCLYYCCC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ShimomuraYIKSKO18,
author = {Naoharu Shimomura and
Hiroaki Yoda and
Tomoaki Inokuchi and
Katsuhiko Koi and
Hideyuki Sugiyama and
Yushi Kato and
Yuichi Ohsawa and
Altansargai Buyandalai and
Satoshi Shirotori and
Soichi Oikawa and
Mariko Shimizu and
Mizue Ishikawa and
Tiwari Ajay and
Atsushi Kurobe},
title = {High-Speed Voltage Control Spintronics Memory (VoCSM) Having Broad
Design Windows},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {83--84},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502420},
doi = {10.1109/VLSIC.2018.8502420},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ShimomuraYIKSKO18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ShinK18,
author = {Dongseok Shin and
Kwang{-}Jin Koh},
title = {A Fast Triple-Interferer Sensor (Detector and Digital Encoder) with
In-Situ Reference Frequency Acquisition at 2.7-to-3.7GHz in 0.13{\(\mu\)}M
{CMOS}},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {29--30},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502294},
doi = {10.1109/VLSIC.2018.8502294},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/ShinK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/SinangilLLC18,
author = {Mahmut E. Sinangil and
Yen{-}Ting Lin and
Hung{-}Jen Liao and
Jonathan Chang},
title = {A 290MV Ultra-Low Voltage One-Port {SRAM} Compiler Design Using a
12T Write Contention and Read Upset Free Bit-Cell in 7NM FinFET Technology},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {13--14},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502419},
doi = {10.1109/VLSIC.2018.8502419},
timestamp = {Wed, 10 Jul 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/SinangilLLC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/Song0CGM18,
author = {Yan Song and
Yan Zhu and
Chi{-}Hang Chan and
Li Geng and
Rui Paulo Martins},
title = {A 77dB {SNDR} 12.5MHz Bandwidth 0-1 {MASH} {\(\sum\)}{\(\Delta\)}
{ADC} Based on the Pipelined-SAR Structure},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {203--204},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502382},
doi = {10.1109/VLSIC.2018.8502382},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/Song0CGM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/SuleimanZCKS18,
author = {Amr Suleiman and
Zhengdong Zhang and
Luca Carlone and
Sertac Karaman and
Vivienne Sze},
title = {Navion: {A} Fully Integrated Energy-Efficient Visual-Inertial Odometry
Accelerator for Autonomous Navigation of Nano Drones},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {133--134},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502279},
doi = {10.1109/VLSIC.2018.8502279},
timestamp = {Wed, 11 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/SuleimanZCKS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/TanCWZRZNLCAUFC18,
author = {Kee Hian Tan and
Ping{-}Chuan Chiang and
Yipeng Wang and
Haibing Zhao and
Arianne Roldan and
Hongyuan Zhao and
Nakul Narang and
Siok{-}Wei Lim and
Declan Carey and
Sai Lalith Chaitanya Ambatipudi and
Parag Upadhyaya and
Yohan Frans and
Ken Chang},
title = {A 112-GB/S {PAM4} Transmitter in 16NM FinFET},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {45--46},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502273},
doi = {10.1109/VLSIC.2018.8502273},
timestamp = {Fri, 31 Jul 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/TanCWZRZNLCAUFC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ToedaFHK18,
author = {Yuta Toeda and
Takumi Fujimaki and
Mototsugu Hamada and
Tadahiro Kuroda},
title = {Fully Integrated OOK-Powered Pad-Less Deep Sub-Wavelength-Sized 5-GHz
{RFID} with On-Chip Antenna Using Adiabatic Logic in 0.18{\(\mu\)}M
{CMOS}},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {27--28},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502283},
doi = {10.1109/VLSIC.2018.8502283},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/ToedaFHK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ToiflMBCFKKLMO18,
author = {Thomas Toifl and
Christian Menolfi and
Matthias Br{\"{a}}ndli and
Alessandro Cevrero and
Pier Andrea Francese and
Marcel A. Kossel and
Lukas Kull and
Danny Luu and
Thomas Morf and
Ilter {\"{O}}zkaya},
title = {A 0.3PJ/Bit 112GB/S {PAM4} 1+0.5D {TX-DFE} Precoder and 8-Tap {FFE}
in 14NM {CMOS}},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {53--54},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502302},
doi = {10.1109/VLSIC.2018.8502302},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ToiflMBCFKKLMO18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/TsaiSCS18,
author = {Tsung{-}Hsien Tsai and
Ruey{-}Bin Sheen and
Chih{-}Hsien Chang and
Robert Bogdan Staszewski},
title = {A 0.2GHz to 4GHz Hybrid {PLL} (ADPLL/Charge-Pump-PLL) in 7NM FinFET
{CMOS} Featuring 0.619PS Integrated Jitter and 0.6US Settling Time
at 2.3MW},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {183--184},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502274},
doi = {10.1109/VLSIC.2018.8502274},
timestamp = {Fri, 27 Dec 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/TsaiSCS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/TsubouchiMSTTMW18,
author = {Yuta Tsubouchi and
Daisuke Miyashita and
Yuji Satoh and
Takashi Toi and
Fumihiko Tachibana and
Makoto Morimoto and
Junji Wadatsumi and
Jun Deguchi},
title = {A 12.8 {GB/S} Daisy Chain-Based Downlink {I/F} Employing Spectrally
Compressed Multi-Band Multiplexing for High-Bandwidth and Large-Capacity
Storage Systems},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {149--150},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502340},
doi = {10.1109/VLSIC.2018.8502340},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/TsubouchiMSTTMW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ValaviRNV18,
author = {Hossein Valavi and
Peter J. Ramadge and
Eric Nestler and
Naveen Verma},
title = {A Mixed-Signal Binarized Convolutional-Neural-Network Accelerator
Integrating Dense Weight Storage and Multiplication for Reduced Data
Movement},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {141--142},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502421},
doi = {10.1109/VLSIC.2018.8502421},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/ValaviRNV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/VazVECMBCWMMLPT18,
author = {Bruno Vaz and
Bob Verbruggen and
Christophe Erdmann and
Diarmuid Collins and
John McGrath and
Ali Boumaalif and
Edward Cullen and
Darragh Walsh and
Alonso Morgado and
Conrado Mesadri and
Brian Long and
Rajitha Pathepuram and
Ronnie De La Torre and
Alvin Manlapat and
Georgios Karyotis and
Dimitris Tsaliagos and
Patrick Lynch and
Peng Lim and
Daire Breathnach and
Brendan Farley},
title = {A 13Bit 5GS/S {ADC} with Time-Interleaved Chopping Calibration in
16NM FinFET},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {99--100},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502306},
doi = {10.1109/VLSIC.2018.8502306},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/VazVECMBCWMMLPT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/WangOTTOIMHST18,
author = {Tong Wang and
Yosuke Ogasawara and
Yuki Tuda and
Tuan Thanh Ta and
Masayoshi Oshiro and
Jun Ihara and
Tatsuhiko Maruyama and
Toru Hashimoto and
Akihide Sai and
Takashi Tokairin},
title = {An 113DB-Link-Budget Bluetooth-5 SoC with an 8dBm 22{\%}-Efficiency
{TX}},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {25--26},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502258},
doi = {10.1109/VLSIC.2018.8502258},
timestamp = {Tue, 04 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/WangOTTOIMHST18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/WangSUMM18,
author = {Biao Wang and
Sai{-}Weng Sin and
Seng{-}Pan U and
Franco Maloberti and
Rui Paulo Martins},
title = {A 550{\(\mathrm{\mu}\)}W 20kHz {BW} 100.8DB {SNDR} Linear-Exponential
Multi-Bit Incremental Converter with 256-cycles in 65NM {CMOS}},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {207--208},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502384},
doi = {10.1109/VLSIC.2018.8502384},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/WangSUMM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/WangWWY18,
author = {Yu{-}Zhe Wang and
Yao{-}Pin Wang and
Yi{-}Chung Wu and
Chia{-}Hsiang Yang},
title = {A 12.6MW 573-2, 901KS/S Reconfigurable Processor for Reconstruction
of Compressively-Sensed Phvsiological Signals},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {261--262},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502321},
doi = {10.1109/VLSIC.2018.8502321},
timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/WangWWY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/WangYKZH18,
author = {Cheng Wang and
Xiang Yi and
Mina Kim and
Yaqing Zhang and
Ruonan Han},
title = {A {CMOS} Molecular Clock Probing 231.061-GHz Rotational Line of {OCS}
with Sub-PPB Long-Term Stability and 66-MW {DC} Power},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {113--114},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502271},
doi = {10.1109/VLSIC.2018.8502271},
timestamp = {Mon, 12 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/WangYKZH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/WhitcombeNSAR18,
author = {Amy Whitcombe and
Borivoje Nikolic and
Farhana Sheikh and
Erkan Alpman and
Ashoke Ravi},
title = {A Dual-Mode Configurable RF-to-Digital Receiver in 16NM FinFET},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {23--24},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502392},
doi = {10.1109/VLSIC.2018.8502392},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/WhitcombeNSAR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/YabuuchiMNT18,
author = {Makoto Yabuuchi and
Masao Morimoto and
Koji Nii and
Shinji Tanaka},
title = {12-NM Fin-FET 3.0G-Search/s 80-Bit {\texttimes} 128-Entry Dual-Port
Ternary {CAM}},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {19--20},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502345},
doi = {10.1109/VLSIC.2018.8502345},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/YabuuchiMNT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/Yang0WSCCBS18,
author = {Kaiyuan Yang and
Qing Dong and
Zhehong Wang and
Yi{-}Chun Shih and
Yu{-}Der Chih and
Tsung{-}Yung Jonathan Chang and
David T. Blaauw and
Dennis Sylvester},
title = {A 28NM Integrated True Random Number Generator Harvesting Entropy
from {MRAM}},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {171--172},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502431},
doi = {10.1109/VLSIC.2018.8502431},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/Yang0WSCCBS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/YinOYLLLW18,
author = {Shouyi Yin and
Peng Ouyang and
Jianxun Yang and
Tianyi Lu and
Xiudong Li and
Leibo Liu and
Shaojun Wei},
title = {An Ultra-High Energy-Efficient Reconfigurable Processor for Deep Neural
Networks with Binary/Ternary Weights in 28NM {CMOS}},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {37--38},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502388},
doi = {10.1109/VLSIC.2018.8502388},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/YinOYLLLW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/YinOZSLLW18,
author = {Shouyi Yin and
Peng Ouyang and
Shixuan Zheng and
Dandan Song and
Xiudong Li and
Leibo Liu and
Shaojun Wei},
title = {A 141 UW, 2.46 PJ/Neuron Binarized Convolutional Neural Network Based
Self-Learning Speech Recognition Processor in 28NM {CMOS}},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {139--140},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502309},
doi = {10.1109/VLSIC.2018.8502309},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/YinOZSLLW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/YoshidaKKGMNH18,
author = {Eiji Yoshida and
S. Kazama and
S. Kuwamura and
S. Gokita and
T. Miyoshi and
Y. Noguchi and
Y. Honda},
title = {Memory Expansion Technology for Large-Scale Data Processing Using
Software-Controlled {SSD}},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {59--60},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502312},
doi = {10.1109/VLSIC.2018.8502312},
timestamp = {Wed, 27 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/YoshidaKKGMNH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/YoshiokaTBYMSO18,
author = {Kentaro Yoshioka and
Yosuke Toyama and
Koichiro Ban and
Daisuke Yashima and
Shigeru Maya and
Akihide Sai and
Kohei Onizuka},
title = {PhaseMAC: {A} 14 {TOPS/W} 8bit {GRO} Based Phase Domain {MAC} Circuit
for in-Sensor-Computed Deep Learning Accelerators},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {263--264},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502291},
doi = {10.1109/VLSIC.2018.8502291},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/YoshiokaTBYMSO18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/YuanYYW0YGLCYL18,
author = {Zhe Yuan and
Jinshan Yue and
Huanrui Yang and
Zhibo Wang and
Jinyang Li and
Yixiong Yang and
Qingwei Guo and
Xueqing Li and
Meng{-}Fan Chang and
Huazhong Yang and
Yongpan Liu},
title = {Sticker: {A} 0.41-62.1 {TOPS/W} 8Bit Neural Network Processor with
Multi-Sparsity Compatible Convolution Arrays and Online Tuning Acceleration
for Fully Connected Layers},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {33--34},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502404},
doi = {10.1109/VLSIC.2018.8502404},
timestamp = {Mon, 27 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/YuanYYW0YGLCYL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ZhangC18,
author = {Aoyang Zhang and
Mike Shuo{-}Wei Chen},
title = {A Sub-Harmonic Switching Digital Power Amplifier with Hybrid Class-G
Operation for Enhancing Power Back-off Efficiency},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {213--214},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502364},
doi = {10.1109/VLSIC.2018.8502364},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/ZhangC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ZhengFAARCM18,
author = {Kevin Zheng and
Yohan Frans and
Sai Lalith Ambatipudi and
Santiago Asuncion and
Hari Teja Reddy and
Ken Chang and
Boris Murmann},
title = {An Inverter-Based Analog Front End for a 56 {GB/S} {PAM4} Wireline
Transceiver in 16NMCMOS},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {269--270},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502377},
doi = {10.1109/VLSIC.2018.8502377},
timestamp = {Tue, 30 Oct 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/ZhengFAARCM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ZhongCK18,
author = {Qian Zhong and
Wooyeol Choi and
Kenneth K. O},
title = {Terahertz {RF} Front-End Employing Even-Order Subharmonic {MOS} Symmetric
Varactor Mixers in 65-NM {CMOS} for Hydration Measurements at 560
GHz},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {211--212},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502297},
doi = {10.1109/VLSIC.2018.8502297},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/ZhongCK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ZhongYBTL18,
author = {Xiaopeng Zhong and
Qian Yu and
Amine Bermak and
Chi{-}Ying Tsui and
May{-}Kay Law},
title = {A 2PJ/Pixel/Direction {MIMO} Processing Based {CMOS} Image Sensor
for Omnidirectional Local Binary Pattern Extraction and Edge Detection},
booktitle = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
pages = {247--248},
publisher = {{IEEE}},
year = {2018},
url = {https://doi.org/10.1109/VLSIC.2018.8502214},
doi = {10.1109/VLSIC.2018.8502214},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ZhongYBTL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsic/2018,
title = {2018 {IEEE} Symposium on {VLSI} Circuits, Honolulu, HI, USA, June
18-22, 2018},
publisher = {{IEEE}},
year = {2018},
url = {https://ieeexplore.ieee.org/xpl/conhome/8484863/proceeding},
isbn = {978-1-5386-4214-6},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/2018.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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