Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDSearch dblp for Publications
export results for "toc:db/conf/vlsic/vlsic2019.bht:"
download as .bib file
@inproceedings{DBLP:conf/vlsic/0004KKKKYK19,
author = {Jinseok Kim and
Jongeun Koo and
Taesu Kim and
Yulhwa Kim and
Hyungjun Kim and
Seunghyun Yoo and
Jae{-}Joon Kim},
title = {Area-Efficient and Variation-Tolerant In-Memory {BNN} Computing using
6T {SRAM} Array},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {118},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778160},
doi = {10.23919/VLSIC.2019.8778160},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/0004KKKKYK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/AbbasAHEGWH19,
author = {Tarek Al Abbas and
Oscar Almer and
Sam W. Hutchings and
Ahmet T. Erdogan and
Istv{\'{a}}n Gy{\"{o}}ngy and
Neale A. W. Dutton and
Robert K. Henderson},
title = {A 128{\texttimes}120 5-Wire 1.96mm\({}^{\mbox{2}}\) 40nm/90nm 3D Stacked
{SPAD} Time Resolved Image Sensor SoC for Microendoscopy},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {260},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777979},
doi = {10.23919/VLSIC.2019.8777979},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/AbbasAHEGWH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/AhmedKALWRTD19,
author = {Khondker Zakir Ahmed and
Harish K. Krishnamurthy and
Charles Augustine and
Xiaosen Liu and
Sheldon Weng and
Krishnan Ravichandran and
James W. Tschanz and
Vivek De},
title = {A Variation-Adaptive Integrated Computational Digital {LDO} in 22nm
{CMOS} with Fast Transient Response},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {124},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778070},
doi = {10.23919/VLSIC.2019.8778070},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/AhmedKALWRTD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/AmeriZGNA19,
author = {Ali Ameri and
Luya Zhang and
Asmaysinh Gharia and
Ali M. Niknejad and
Mekhail Anwar},
title = {A 114GHz Biosensor with Integrated Dielectrophoresis for Single Cell
Characterization},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {314},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778194},
doi = {10.23919/VLSIC.2019.8778194},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/AmeriZGNA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/BhargavaKPNYTBF19,
author = {Pavan Bhargava and
Taehwan Kim and
Christopher V. Poulton and
Jelena Notaros and
Ami Yaacobi and
Erman Timurdogan and
Christopher Baiocco and
Nicholas Fahrenkopf and
Seth Kruger and
Tat Ngai and
Yukta Timalsina and
Michael R. Watts and
Vladimir Stojanovic},
title = {Fully Integrated Coherent LiDAR in 3D-Integrated Silicon Photonics/65nm
{CMOS}},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {262},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778154},
doi = {10.23919/VLSIC.2019.8778154},
timestamp = {Wed, 30 Oct 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/BhargavaKPNYTBF19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/BianchiMPMAI19,
author = {Stefano Bianchi and
I. Mu{\~{n}}oz{-}Mart{\'{\i}}n and
Giacomo Pedretti and
Octavian Melnic and
Stefano Ambrogio and
Daniele Ielmini},
title = {Energy-efficient continual learning in hybrid supervised-unsupervised
neural networks with {PCM} synapses},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {1--2},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778001},
doi = {10.23919/VLSIC.2019.8778001},
timestamp = {Wed, 18 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/BianchiMPMAI19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/BindraALN19,
author = {Harijot Singh Bindra and
Anne{-}Johan Annema and
Simon M. Louwsma and
Bram Nauta},
title = {A 0.2 - 8 MS/s 10b flexible {SAR} {ADC} achieving 0.35 - 2.5 fJ/conv-step
and using self-quenched dynamic bias comparator},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {74},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778093},
doi = {10.23919/VLSIC.2019.8778093},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/BindraALN19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/BowmanGANJYPHRC19,
author = {Keith A. Bowman and
Samantak Gangopadhyay and
Francois Atallah and
Hoan Nguyen and
Jihoon Jeong and
Daniel Yingling and
Anthony Polomik and
Mahesh Harinath and
Nathaniel Reeves and
Amer Cassier and
Brad Appel and
Arijit Raychowdhury},
title = {A 7nm Leakage-Current-Supply Circuit for {LDO} Dropout Voltage Reduction},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {126},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778148},
doi = {10.23919/VLSIC.2019.8778148},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/BowmanGANJYPHRC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/CakirCCTMTSB19,
author = {Cagla Cakir and
Andy W. Chen and
Y. K. Chong and
Sriram Thyagarajan and
Mark P. McCartney and
Peixuan Tan and
Yulin Shi and
Mudit Bhargava},
title = {A 4GHz 16nm {SRAM} Architecture with Low-Power Features for Heterogeneous
Computing Platforms},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {112},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778108},
doi = {10.23919/VLSIC.2019.8778108},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/CakirCCTMTSB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/CenciBRGLMB19,
author = {Pierluigi Cenci and
Muhammed Bolatkale and
Robert Rutten and
M. Ganzerli and
Gerard Lassche and
Kofi A. A. Makinwa and
Lucien J. Breems},
title = {A 3.2mW SAR-assisted CT{\(\Delta\)}{\(\sum\)} {ADC} with 77.5dB {SNDR}
and 40MHz {BW} in 28nm {CMOS}},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {230},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778176},
doi = {10.23919/VLSIC.2019.8778176},
timestamp = {Fri, 03 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/CenciBRGLMB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/CerqueiraRPPKS19,
author = {Joao Pedro Cerqueira and
Thomas J. Repetti and
Yu Pu and
Shivam Priyadarshi and
Martha A. Kim and
Mingoo Seok},
title = {Catena: {A} 0.5-V Sub-0.4-mW 16-Core Spatial Array Accelerator for
Mobile and Embedded Computing},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {54},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777987},
doi = {10.23919/VLSIC.2019.8777987},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/CerqueiraRPPKS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ChaeCLCYNHLLSSL19,
author = {Kwanyeob Chae and
JongRyun Choi and
Hyungkwon Lee and
Jinho Choi and
Shinyoung Yi and
Yoonjee Nam and
Sangyun Hwang and
Joohyung Lee and
Won Lee and
Kihwan Seong and
Joohee Shin and
Soo{-}Min Lee and
Seokkyun Ko and
Jihun Oh and
Billy Koo and
Sanghune Park and
Jongshin Shin and
Hyungjong Ko},
title = {An 8nm All-Digital 7.3Gb/s/pin {LPDDR5} {PHY} with an Approximate
Delay Compensation Scheme},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {96},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777959},
doi = {10.23919/VLSIC.2019.8777959},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ChaeCLCYNHLLSSL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ChappidiS19,
author = {ChandraKanth R. Chappidi and
Kaushik Sengupta},
title = {A 26-42 GHz Broadband, Back-off Efficient and Vswr Tolerant {CMOS}
Power Amplifier Architecture for 5G Applications},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {22},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778095},
doi = {10.23919/VLSIC.2019.8778095},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ChappidiS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ChenYHCH19,
author = {Po{-}Han Chen and
Shu{-}Wen Yang and
Shih{-}Yao Huang and
Li{-}De Chen and
Chao{-}Tsung Huang},
title = {A 250mW 5.4G-Novel-Pixel/s Photorealistic Refocusing Processor for
Full-HD Five-Camera Applications},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {154},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778155},
doi = {10.23919/VLSIC.2019.8778155},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ChenYHCH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ChenYSHTH19,
author = {Wei{-}Chih Chen and
Shu{-}Chun Yang and
Yu{-}Nan Shih and
Wen{-}Hung Huang and
Chien{-}Chun Tsai and
Kenny Cheng{-}Hsiang Hsieh},
title = {A 56Gb/s {PAM-4} Receiver with Voltage Pre-Shift {CTLE} and 10-Tap
{DFE} of Tap-1 Speculation in 7nm FinFET},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {272},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777992},
doi = {10.23919/VLSIC.2019.8777992},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ChenYSHTH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ChengGNKZKTL19,
author = {Lin Cheng and
Xinyuan Ge and
Wai Chiu Ng and
Wing{-}Hung Ki and
Jiawei Zheng and
Tsz Fai Kwok and
Chi{-}Ying Tsui and
Ming Liu},
title = {A 6.78MHz 92.3{\%}-Peak-Efficiency Single-Stage Wireless Charger with
{CC-CV} Charging and On-Chip Bootstrapping Techniques},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {320},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777990},
doi = {10.23919/VLSIC.2019.8777990},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/ChengGNKZKTL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ChienMSA19,
author = {Jun{-}Chau Chien and
Peter L. Mage and
H. Tom Soh and
Amin Arbabian},
title = {An Aptamer-based Electrochemical-Sensing Implant for Continuous Therapeutic-
Drug Monitoring in vivo},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {312},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777991},
doi = {10.23919/VLSIC.2019.8777991},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ChienMSA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/DisegniAMCCZFVC19,
author = {Fabio Disegni and
Roberto Annunziata and
A. Molgora and
G. Campardo and
Paolo Cappelletti and
P. Zuliani and
P. Ferreira and
A. Ventre and
G. Castagna and
Andreia Cathelin and
Anna Gandolfo and
F. Goller and
S. Malhi and
D. Manfr{\`{e}} and
Alfonso Maurelli and
C. Torti and
Franck Arnaud and
M. Carf{\`{\i}} and
M. Perroni and
M. Caruso and
S. Pezzini and
G. Piazza and
Olivier Weber and
M. Peri},
title = {Embedded {PCM} macro for automotive-grade microcontroller in 28nm
{FD-SOI}},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {204},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778129},
doi = {10.23919/VLSIC.2019.8778129},
timestamp = {Mon, 09 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/DisegniAMCCZFVC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/DorranceLBDLKAC19,
author = {Richard Dorrance and
Renzhi Liu and
K. T. Asma Beevi and
Deepak Dasalukunte and
Mario A. Santana Lopez and
Vinod Kristem and
Shahrnaz Azizi and
Brent R. Carlton},
title = {An Ultra-Low Power, Fully Integrated Wake-Up Receiver and Digital
Baseband with All-Digital Impairment Correction and -92.4dBm Sensitivity
for 802.11ba},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {80},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778013},
doi = {10.23919/VLSIC.2019.8778013},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/DorranceLBDLKAC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/DuttaKCGJD19,
author = {Sourav Dutta and
A. Khanna and
Wriddhi Chakraborty and
J. Gomez and
S. Joshi and
Suman Datta},
title = {Spoken vowel classification using synchronization of phase transition
nano-oscillators},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {128},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777988},
doi = {10.23919/VLSIC.2019.8777988},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/DuttaKCGJD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/FujibayashiT19,
author = {Takeji Fujibayashi and
Yohsuke Takeda},
title = {A 76- to 81-GHz, 0.6{\textdegree} rms Phase Error Multi-channel Transmitter
with a Novel Phase Detector and Compensation Technique},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {16},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778158},
doi = {10.23919/VLSIC.2019.8778158},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/FujibayashiT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/FujiiIKYSTZYSK19,
author = {Shosuke Fujii and
Reika Ichihara and
Takuya Konno and
Marina Yamaguchi and
Harumi Seki and
Hiroki Tanaka and
Dandan Zhao and
Yoko Yoshimura and
Masumi Saitoh and
Masato Koyama},
title = {Ag Ionic Memory Cell Technology for Terabit-Scale High-DensityApplication},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {188},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778071},
doi = {10.23919/VLSIC.2019.8778071},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/FujiiIKYSTZYSK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/FujitaTTI19,
author = {Shinobu Fujita and
Satoshi Takaya and
Susumu Takeda and
Kazutaka Ikegami},
title = {Circuit And Systems Based on Advanced {MRAM} for Near Future Computing
Applications},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {278},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778045},
doi = {10.23919/VLSIC.2019.8778045},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/FujitaTTI19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/GallagherCCHSWB19,
author = {William J. Gallagher and
Eric Chien and
Tien{-}Wei Chiang and
Jian{-}Cheng Huang and
Meng{-}Chun Shih and
C. Y. Wang and
Christine Bair and
George Lee and
Yi{-}Chun Shih and
Chia{-}Fu Lee and
Roger Wang and
Kuei{-}Hung Shen and
J. J. Wu and
Wayne Wang and
Harry Chuang},
title = {Recent Progress and Next Directions for Embedded {MRAM} Technology},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {190},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777932},
doi = {10.23919/VLSIC.2019.8777932},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/GallagherCCHSWB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/GarelloYHCSSSCR19,
author = {Kevin Garello and
Farrukh Yasin and
Hubert Hody and
S. Couet and
Laurent Souriau and
Shamin H. Sharifi and
Johan Swerts and
Robert Carpenter and
Sidharth Rao and
Wonsub Kim and
J. Wu and
K. K. V. Sethu and
M. Pak and
N. Jossart and
D. Crotti and
Arnaud Furn{\'{e}}mont and
Gouri Sankar Kar},
title = {Manufacturable 300mm platform solution for Field-Free Switching {SOT-MRAM}},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {194},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778100},
doi = {10.23919/VLSIC.2019.8778100},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/GarelloYHCSSSCR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/GiraldoLBhV19,
author = {Juan Sebastian Piedrahita Giraldo and
Steven Lauwereins and
Komail M. H. Badami and
Hugo Van hamme and
Marian Verhelst},
title = {18{\(\mu\)}W SoC for near-microphone Keyword Spotting and Speaker
Verification},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {52},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777994},
doi = {10.23919/VLSIC.2019.8777994},
timestamp = {Wed, 02 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/GiraldoLBhV19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/GonenKVM19,
author = {Burak G{\"{o}}nen and
Shoubhik Karmakar and
Robert H. M. van Veldhoven and
Kofi A. A. Makinwa},
title = {A Low Power Continuous-Time Zoom {ADC} for Audio Applications},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {224},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778021},
doi = {10.23919/VLSIC.2019.8778021},
timestamp = {Tue, 06 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/GonenKVM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/GuoLZWOKCCLLCWY19,
author = {Ruiqi Guo and
Yonggang Liu and
Shixuan Zheng and
Ssu{-}Yen Wu and
Peng Ouyang and
Win{-}San Khwa and
Xi Chen and
Jia{-}Jing Chen and
Xiudong Li and
Leibo Liu and
Meng{-}Fan Chang and
Shaojun Wei and
Shouyi Yin},
title = {A 5.1pJ/Neuron 127.3us/Inference RNN-based Speech Recognition Processor
using 16 Computing-in-Memory {SRAM} Macros in 65nm {CMOS}},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {120},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778028},
doi = {10.23919/VLSIC.2019.8778028},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/GuoLZWOKCCLLCWY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/GuoMSWM19,
author = {Mingqiang Guo and
Jiaji Mao and
Sai{-}Weng Sin and
He Gong Wei and
Rui Paulo Martins},
title = {A 29mW 5GS/s Time-interleaved {SAR} {ADC} achieving 48.5dB {SNDR}
With Fully-Digital Timing-Skew Calibration Based on Digital-Mixing},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {76},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778077},
doi = {10.23919/VLSIC.2019.8778077},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/GuoMSWM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/HanCC19,
author = {Hyeonho Han and
Woojun Choi and
Youngcheol Chae},
title = {A 0.02mm\({}^{\mbox{2}}\) 100dB-DR Impedance Monitoring {IC} with
PWM-Dual {GRO} Architecture},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {60},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778126},
doi = {10.23919/VLSIC.2019.8778126},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/HanCC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/HanLLY19,
author = {Donghyeon Han and
Jinsu Lee and
Jinmook Lee and
Hoi{-}Jun Yoo},
title = {A 1.32 {TOPS/W} Energy Efficient Deep Neural Network Learning Processor
with Direct Feedback Alignment based Heterogeneous Core Architecture},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {304},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778006},
doi = {10.23919/VLSIC.2019.8778006},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/HanLLY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/HayashiTYY19,
author = {Masato Hayashi and
Takashi Takemoto and
Chihiro Yoshimura and
Masanao Yamaoka},
title = {A Cloud-ready Scalable Annealing Processor for Solving Large-scale
Combinatorial Optimization Problems},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {148},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778131},
doi = {10.23919/VLSIC.2019.8778131},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/HayashiTYY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/HeoKLLMKBYYKKPP19,
author = {Jin{-}Seok Heo and
Kihan Kim and
Dong{-}Hoon Lee and
Chang{-}Kyo Lee and
Daesik Moon and
Kiho Kim and
Jin{-}Hyeok Baek and
Sung{-}Woo Yoon and
Hui{-}Kap Yang and
Kyungryun Kim and
Youngjae Kim and
Bokgue Park and
Su{-}Jin Park and
Joung{-}Wook Moon and
Jae{-}Hyung Lee and
Yun{-}Sik Park and
Soobong Jang and
Seok{-}Hun Hyun and
Hyuck{-}Joon Kwon and
Jung{-}Hwan Choi and
Young{-}Soo Sohn and
Seung{-}Jun Bae and
Kwang{-}Il Park and
Jung{-}Bae Lee},
title = {A 5Gb/s/pin 16Gb {LPDDR4/4X} Reconfigurable {SDRAM} with Voltage-High
Keeper and a Prediction-based Fast-tracking {ZQ} Calibration},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {114},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778102},
doi = {10.23919/VLSIC.2019.8778102},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/HeoKLLMKBYYKKPP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/HsiehCCCC19,
author = {E. R. Hsieh and
C. W. Chang and
C. C. Chuang and
H. W. Chen and
Steve S. Chung},
title = {The Demonstration of Gate Dielectric-fuse 4kb {OTP} Memory Feasible
for Embedded Applications in High-k Metal-gate {CMOS} Generations
and Beyond},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {208},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778094},
doi = {10.23919/VLSIC.2019.8778094},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/HsiehCCCC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/Hsu0KAKKSSMKD19,
author = {Steven Hsu and
Amit Agarwal and
Monodeep Kar and
Mark A. Anders and
Himanshu Kaul and
Raghavan Kumar and
Sudhir Satpathy and
Vikram B. Suresh and
Sanu Mathew and
Ram Krishnamurthy and
Vivek De},
title = {A Microwatt-Class Always-On Sensor Fusion Engine Featuring Ultra-Low-Power
{AOI} Clocked Circuits in 14nm {CMOS}},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {50},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777978},
doi = {10.23919/VLSIC.2019.8777978},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/Hsu0KAKKSSMKD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/HsuS19,
author = {Chen{-}Kai Hsu and
Nan Sun},
title = {A 75.8dB-SNDR Pipeline {SAR} {ADC} with 2\({}^{\mbox{nd}}\)-order
Interstage Gain Error Shaping},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {68},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778032},
doi = {10.23919/VLSIC.2019.8778032},
timestamp = {Mon, 25 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/HsuS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/HuangK19,
author = {Hung{-}Yi Huang and
Tai{-}Haur Kuo},
title = {A 0.07mm\({}^{\mbox{2}}\) 210mW Single-1.1V-Supply 14-bit 10GS/s {DAC}
with Concentric Parallelogram Routing and Output Impedance Compensation},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {136},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778067},
doi = {10.23919/VLSIC.2019.8778067},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/HuangK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/HuangWCS19,
author = {Wei{-}Hsiang Huang and
Su{-}Hao Wu and
Zhi{-}Xin Chen and
Yun{-}Shiang Shu},
title = {An Amplifier-Less Calibration-Free {SAR} {ADC} Achieving {\textgreater}100dB
{SNDR} for Multi-Channel {ECG} Acquisition with 667mVpp Linear Input
Range},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {70},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777944},
doi = {10.23919/VLSIC.2019.8777944},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/HuangWCS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/HwangCDJKPKJ19,
author = {Jeongho Hwang and
Hong{-}Seok Choi and
Hyungrok Do and
Gyu{-}Seob Jeong and
Daehyun Koh and
Kwanseo Park and
Sungwoo Kim and
Deog{-}Kyoon Jeong},
title = {A 64Gb/s 2.29pJ/b {PAM-4} {VCSEL} Transmitter With 3-Tap Asymmetric
{FFE} in 65nm {CMOS}},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {268},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777952},
doi = {10.23919/VLSIC.2019.8777952},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/HwangCDJKPKJ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/IshizuYFIFAAMKF19,
author = {Takahiko Ishizu and
Yuto Yakubo and
Kazuma Furutani and
Atsuo Isobe and
Masashi Fujita and
Tomoaki Atsumi and
Yoshinori Ando and
Tsutomu Murakawa and
Kiyoshi Kato and
Masahiro Fujita and
Shunpei Yamazaki},
title = {A 48 MHz 880-nW Standby Power Normally-Off {MCU} with 1 Clock Full
Backup and 4.69-{\(\mu\)}s Wakeup Featuring 60-nm Crystalline In-Ga-Zn
Oxide BEOL-FETs},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {48},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778076},
doi = {10.23919/VLSIC.2019.8778076},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/IshizuYFIFAAMKF19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/JangRPAJHK19,
author = {E{-}San Jang and
Min{-}Woo Ryu and
R. Patel and
S. H. Ahn and
H. J. Jeon and
K. J. Han and
K. R. Kim},
title = {Record-High Performance Trantenna Based On Asymmetric Nano-Ring Fet
For Polarization-Independent Large-Scale/Real-Time Thz Imaging},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {160},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778116},
doi = {10.23919/VLSIC.2019.8778116},
timestamp = {Wed, 14 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/JangRPAJHK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/JeonJCCSJKJ19,
author = {Yeseul Jeon and
Chongsoo Jung and
Song{-}I Cheon and
Hyungjoo Cho and
Ji{-}Hoon Suh and
Hyuntak Jeon and
Seok{-}Tae Koh and
Minkyu Je},
title = {A 100Mb/s Galvanically-Coupled Body-Channel-Communication Transceiver
with 4.75pJ/b {TX} and 26.8 pJ/b {RX} for Bionic Arms},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {292},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778040},
doi = {10.23919/VLSIC.2019.8778040},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/JeonJCCSJKJ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/JeonKLKHKPS19,
author = {Cheonhoo Jeon and
Jahyun Koo and
Kyongsu Lee and
Su{-}Kyoung Kim and
Sei Kwang Hahn and
Byungsub Kim and
Hong{-}June Park and
Jae{-}Yoon Sim},
title = {A 143nW Glucose-Monitoring Smart Contact Lens {IC} with a Dual-Mode
Transmitter for Wireless-Powered Backscattering and RF-Radiated Transmission
Using a Single Loop Antenna},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {294},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777984},
doi = {10.23919/VLSIC.2019.8777984},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/JeonKLKHKPS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/JungPJGKWLCW19,
author = {Doohwan Jung and
Jong Seok Park and
Gregory Villiam Junek and
Sandra Ivonne Grijalva and
Sagar R. Kumashi and
Adam Y. Wang and
Sensen Li and
Hee Cheol Cho and
Hua Wang},
title = {A 21952-Pixel Multi-Modal {CMOS} Cellular Sensor Array with 1568-Pixel
Parallel Recording and 4-Point Impedance Sensing},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {62},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778043},
doi = {10.23919/VLSIC.2019.8778043},
timestamp = {Fri, 19 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/JungPJGKWLCW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/KandaKTOTYNIKK19,
author = {Akihiko Kanda and
Takashi Kurafuji and
Koichi Takeda and
Tomoya Ogawa and
Yasuhiko Taito and
Kazuo Yoshihara and
Masaya Nakano and
Takashi Ito and
Hiroyuki Kondo and
Takashi Kono},
title = {A 24MB Embedded Flash System Based on 28nm {SG-MONOS} Featuring 240MHz
Read Operations and Robust Over-The-Air Software Update for Automotive},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {210},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778107},
doi = {10.23919/VLSIC.2019.8778107},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/KandaKTOTYNIKK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/KangLOJKAKSJSB19,
author = {Taewook Kang and
Inhee Lee and
Sechang Oh and
Tae{-}Kwang Jang and
Yejoong Kim and
Hyochan Ahn and
Gyouho Kim and
Se{-}Un Shin and
Seokhyeon Jeong and
Dennis Sylvester and
David T. Blaauw},
title = {A 1.74.12 mm\({}^{\mbox{3}}\) Fully Integrated pH Sensor for Implantable
Applications using Differential Sensing and Drift-Compensation},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {310},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778184},
doi = {10.23919/VLSIC.2019.8778184},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/KangLOJKAKSJSB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/KeelJKKKBCSKACJ19,
author = {Min{-}Sun Keel and
Young{-}Gu Jin and
Youngchan Kim and
Daeyun Kim and
Yeomyung Kim and
Myunghan Bae and
Bumsik Chung and
Sooho Son and
Hogyun Kim and
Taemin An and
Sung{-}Ho Choi and
Taesub Jung and
Yonghun Kwon and
Sungyoung Seo and
Sae{-}Young Kim and
Kwanghyuk Bae and
Seung{-}Chul Shin and
Myoungoh Ki and
Chang{-}Rok Moon and
Hyunsurk Ryu},
title = {A 640{\texttimes}480 Indirect Time-of-Flight {CMOS} Image Sensor with
4-tap 7-{\(\mu\)}m Global-Shutter Pixel and Fixed-Pattern Phase Noise
Self-Compensation Scheme},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {258},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778090},
doi = {10.23919/VLSIC.2019.8778090},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/KeelJKKKBCSKACJ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/KimJRKR19,
author = {Woo{-}Cheol Kim and
Dong{-}Shin Jo and
Yi{-}Ju Roh and
Ye{-}Dam Kim and
Seung{-}Tak Ryu},
title = {A 6b 28GS/s Four-channel Time-interleaved Current-Steering {DAC} with
Background Clock Phase Calibration},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {138},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778096},
doi = {10.23919/VLSIC.2019.8778096},
timestamp = {Sat, 05 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/KimJRKR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/KimK19,
author = {Dong{-}Kyu Kim and
Hyun{-}Sik Kim},
title = {A 300mA BGR-Recursive Low-Dropout Regulator Achieving 102-to-80dB
{PSR} at Frequencies from 100Hz to 0.1MHz with Current Efficiency
of 99.98{\%}},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {132},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778081},
doi = {10.23919/VLSIC.2019.8778081},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/KimK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/KimKPSS19,
author = {Sung Justin Kim and
Dongkwun Kim and
Yu Pu and
Chunlei Shi and
Mingoo Seok},
title = {A 0.5-1V Input Event-Driven Multiple Digital Low-Dropout-Regulator
System for Supporting a Large Digital Load},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {128},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778117},
doi = {10.23919/VLSIC.2019.8778117},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/KimKPSS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/Ko19,
author = {Seung{-}Hoon Ko},
title = {An Automatic Ear Detection Technique in Capacitive Sensing Readout
{IC} Using Cascaded Classifiers and Hovering function},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {218},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778125},
doi = {10.23919/VLSIC.2019.8778125},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/Ko19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/KoKSCH019,
author = {Chen{-}Ting Ko and
Ting{-}Kuei Kuan and
Ruei{-}Pin Shen and
Chih{-}Hsien Chang and
Kenny Hsieh and
Mark Chen},
title = {A 387.6fs Integrated Jitter and -80dBc Reference Spurs Ring based
{PLL} with Track- and-Hold Charge Pump and Automatic Loop Gain Control
in 7nm FinFET {CMOS}},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {164},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777946},
doi = {10.23919/VLSIC.2019.8777946},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/KoKSCH019.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/KoSKLYJLKJ19,
author = {Han{-}Gon Ko and
Soyeong Shin and
Chan{-}Ho Kye and
Sang{-}Yoon Lee and
Jaekwang Yun and
Hae{-}Kang Jung and
Doobock Lee and
Suhwan Kim and
Deog{-}Kyoon Jeong},
title = {A 370-fJ/b, 0.0056 mm\({}^{\mbox{2}}\)/DQ, 4.8-Gb/s {DQ} Receiver
for {HBM3} with a Baud-Rate Self-Tracking Loop},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {94},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778082},
doi = {10.23919/VLSIC.2019.8778082},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/KoSKLYJLKJ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/KrupnikPLSEKLVD19,
author = {Yoel Krupnik and
Yevgeny Perelman and
Itamar Levin and
Yosi Sanhedrai and
Roee Eitan and
Ahmad Khairi and
Yoni Landau and
Udi Virobnik and
Noam Dolev and
Alon Meisler and
Ariel Cohen},
title = {112 Gb/s {PAM4} {ADC} Based {SERDES} Receiver for Long-Reach Channels
in 10nm Process},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {266},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778136},
doi = {10.23919/VLSIC.2019.8778136},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/KrupnikPLSEKLVD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/KumarSKSAKAHCKD19,
author = {Raghavan Kumar and
Vikram B. Suresh and
Monodeep Kar and
Sudhir Satpathy and
Mark A. Anders and
Himanshu Kaul and
Amit Agarwal and
Steven Hsu and
Gregory K. Chen and
Ram Krishnamurthy and
Vivek De and
Sanu Mathew},
title = {A 4900{\texttimes}m\({}^{\mbox{2}}\) 839Mbps Side-Channel Attack Resistant
{AES-128} in 14nm {CMOS} with Heterogeneous Sboxes, Linear Masked
MixColumns and Dual-Rail Key Addition},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {234},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778041},
doi = {10.23919/VLSIC.2019.8778041},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/KumarSKSAKAHCKD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/LeeB19,
author = {Inhee Lee and
David T. Blaauw},
title = {A 31 pW-to-113 nW Hybrid {BJT} and {CMOS} Voltage Reference with 3.6{\%}
{\(\pm\)}3{\(\sigma\)}-inaccuracy from 0\({}^{\mbox{{\unicode{9675}}}}\)C
to 170 \({}^{\mbox{{\unicode{9675}}}}\)C for Low-Power High-Temperature
IoT Systems},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {142},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778113},
doi = {10.23919/VLSIC.2019.8778113},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/LeeB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/LeeBLC19,
author = {Jeonghyun Lee and
Jooeun Bang and
Younghyun Lim and
Jaehyouk Choi},
title = {A 0.5V-VIN, 0.29ps-Transient-FOM, and Sub-2mV-Accuracy Adaptive-Sampling
Digital {LDO} Using Single-VCO-Based Edge-Racing Time Quantizer},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {130},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777999},
doi = {10.23919/VLSIC.2019.8777999},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/LeeBLC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/LeeHCLLT19,
author = {Cheng{-}Yen Lee and
Tzu{-}Ping Huang and
Ke{-}Horng Chen and
Ying{-}Hsi Lin and
Shian{-}Ru Lin and
Tsung{-}Yen Tsai},
title = {A High Current efficiency Stacked Digital Low Dropout Array with True-Random-Noise
Injection and Ultralow Output Ripple for Power-Side Channel Attack
Protection},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {322},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778069},
doi = {10.23919/VLSIC.2019.8778069},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/LeeHCLLT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/LeeLKK19,
author = {Daewoong Lee and
Dongil Lee and
Yong{-}Hun Kim and
Lee{-}Sup Kim},
title = {A 0.87 {V} 12.5 Gb/s Clock-Path Feedback Equalization Receiver with
Unfixed Tap Weighting Property in 65 nm {CMOS}},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {196},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777968},
doi = {10.23919/VLSIC.2019.8777968},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/LeeLKK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/LeeLKKPJ19,
author = {Jinhyung Lee and
Kwangho Lee and
Hyojun Kim and
Byungmin Kim and
Kwanseo Park and
Deog{-}Kyoon Jeong},
title = {A 0.1pJ/b/dB 1.62-to-10.8Gb/s Video Interface Receiver with Fully
Adaptive Equalization Using Un-Even Data Level},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {198},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778084},
doi = {10.23919/VLSIC.2019.8778084},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/LeeLKKPJ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/LeeMKPB19,
author = {Inhee Lee and
Eunseong Moon and
Yejoong Kim and
Jamie Phillips and
David T. Blaauw},
title = {A 10mm\({}^{\mbox{3}}\) Light-Dose Sensing IoT\({}^{\mbox{2}}\) System
With 35-To-339nW 10-To-300klx Light-Dose-To-Digital Converter},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {180},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778007},
doi = {10.23919/VLSIC.2019.8778007},
timestamp = {Tue, 06 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/LeeMKPB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/LeePCCJKCKJ19,
author = {Taeju Lee and
Jee{-}Ho Park and
Ji{-}Hyoung Cha and
Namsun Chou and
Doojin Jang and
Ji{-}Hoon Kim and
Il{-}Joo Cho and
Seong{-}Jin Kim and
Minkyu Je},
title = {A Multimodal Multichannel Neural Activity Readout {IC} with 0.7{\(\mu\)}W/Channel
Ca\({}^{\mbox{2+}}\)-Probe-Based Fluorescence Recording and Electrical
Recording},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {290},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778042},
doi = {10.23919/VLSIC.2019.8778042},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/LeePCCJKCKJ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/LeeSLLKY19,
author = {Juhyoung Lee and
Dongjoo Shin and
Jinsu Lee and
Jinmook Lee and
Sanghoon Kang and
Hoi{-}Jun Yoo},
title = {A Full {HD} 60 fps {CNN} Super Resolution Processor with Selective
Caching based Layer Fusion for Mobile Devices},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {302},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778104},
doi = {10.23919/VLSIC.2019.8778104},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/LeeSLLKY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/LiCTWCCNJVP19,
author = {Jing Li and
Zhao Chen and
Mingliang Tan and
Douwe van Willigen and
Chao Chen and
Zu{-}yao Chang and
Emile Noothout and
Nico de Jong and
Martin D. Verweij and
Michiel A. P. Pertijs},
title = {A 1.54mW/Element 150{\(\mu\)}m-Pitch-Matched Receiver {ASIC} with
Element-Level SAR/Shared-Single-Slope Hybrid ADCs for Miniature 3D
Ultrasound Probes},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {220},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778200},
doi = {10.23919/VLSIC.2019.8778200},
timestamp = {Fri, 24 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/LiCTWCCNJVP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/LiLCD19,
author = {Chenghan Li and
Luca Longinotti and
Federico Corradi and
Tobi Delbr{\"{u}}ck},
title = {A 132 by 104 10{\(\mu\)}m-Pixel 250{\(\mu\)}W 1kefps Dynamic Vision
Sensor with Pixel-Parallel Noise and Spatial Redundancy Suppression},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {216},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778050},
doi = {10.23919/VLSIC.2019.8778050},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/LiLCD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/LiN19,
author = {Yi{-}An Li and
Ali M. Niknejad},
title = {A 138Fsrms-Integrated-Jitter and -249dB-FoM Clock Multiplier with
-51dBc Spur Using {A} Digital Spur Calibration Technique in 28-nm
{CMOS}},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {42},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777937},
doi = {10.23919/VLSIC.2019.8777937},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/LiN19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/LiRC19,
author = {Shuo Li and
Abhishek Roy and
Benton H. Calhoun},
title = {A Piezoelectric Energy-Harvesting System with Parallel-SSHI Rectifier
and Integrated {MPPT} Achieving 417{\%} Energy-Extraction Improvement
and 97{\%} Tracking Efficiency},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {324},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778144},
doi = {10.23919/VLSIC.2019.8778144},
timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/LiRC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/LinHOWCLLC19,
author = {Yen{-}An Lin and
Tzu{-}Ping Huang and
You{-}Zheng Ou{-}Yang and
Zheng{-}Ru Wu and
Ke{-}Horng Chen and
Ying{-}Hsi Lin and
Ming{-}Hsien Lin and
Hung{-}Ting Chou},
title = {A Right-Half-Plane Zero-Free Buck-Boost {DC-DC} Converter with 97.46{\%}
High Efficiency and Low Output Voltage Ripple},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {174},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778075},
doi = {10.23919/VLSIC.2019.8778075},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/LinHOWCLLC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/LinHTTHCHHCGFRL19,
author = {Mu{-}Shan Lin and
Tze{-}Chiang Huang and
Chien{-}Chun Tsai and
King{-}Ho Tam and
Kenny Cheng{-}Hsiang Hsieh and
Tom Chen and
Wen{-}Hung Huang and
Jack Hu and
Yu{-}Chi Chen and
Sandeep Kumar Goel and
Chin{-}Ming Fu and
Stefan Rusu and
Chao{-}Chieh Li and
Sheng{-}Yao Yang and
Mei Wong and
Shu{-}Chun Yang and
Frank Lee},
title = {A 7nm 4GHz Arm\({}^{\mbox{{\textregistered}}}\)-core-based CoWoS\({}^{\mbox{{\textregistered}}}\)
Chiplet Design for High Performance Computing},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {28},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778161},
doi = {10.23919/VLSIC.2019.8778161},
timestamp = {Thu, 02 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/LinHTTHCHHCGFRL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/LinJA19,
author = {Longyang Lin and
Saurabh Jain and
Massimo Alioto},
title = {Integrated Power Management and Microcontroller for Ultra-Wide Power
Adaptation down to nW},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {178},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778085},
doi = {10.23919/VLSIC.2019.8778085},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/LinJA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/LinXSBKCHTH19,
author = {Qiuyang Lin and
Jiawei Xu and
Shuang Song and
Arjan Breeschoten and
Mario Konijnenburg and
Mingyi Chen and
Chris Van Hoof and
Filip Tavernier and
Nick Van Helleputte},
title = {A 196{\(\mu\)}W, Reconfigurable Light-to-Digital Converter with 119dB
Dynamic Range, for Wearable {PPG/NIRS} Sensors},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {58},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778004},
doi = {10.23919/VLSIC.2019.8778004},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/LinXSBKCHTH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/LiuL19,
author = {Xiaolong Liu and
Howard C. Luong},
title = {A 270-Ghz Fully-Integrated Frequency Synthesizer in 65nm {CMOS}},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {40},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777982},
doi = {10.23919/VLSIC.2019.8777982},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/LiuL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/MaksimovicWBKMS19,
author = {Filip Maksimovic and
Brad Wheeler and
David C. Burnett and
Osama Khan and
Sahar M. Mesri and
Ioana Suciu and
Lydia Lee and
Alex Moreno and
Arvind Sundararajan and
Bob L. Zhou and
Rachel Zoll and
Andrew Ng and
Tengfei Chang and
Xavier Vilajosana and
Thomas Watteyne and
Ali M. Niknejad and
Kristofer S. J. Pister},
title = {A Crystal-Free Single-Chip Micro Mote with Integrated 802.15.4 Compatible
Transceiver, sub-mW {BLE} Compatible Beacon Transmitter, and Cortex
{M0}},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {88},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777971},
doi = {10.23919/VLSIC.2019.8777971},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/MaksimovicWBKMS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/MatsubaraNKMSIA19,
author = {Ken Matsubara and
Tsutomu Nagasawa and
Yoshinobu Kaneda and
Hidenori Mitani and
Hiroshi Sato and
Takashi Iwase and
Yasunobu Aoki and
Keiichi Maekawa and
Hideaki Yamakoshi and
Takashi Ito and
Hiroyuki Kondo and
Takashi Kono},
title = {A 65nm Silicon-on-Thin-Box {(SOTB)} Embedded 2T-MONOS Flash Achieving
0.22 pJ/bit Read Energy with 64 MHz Access for IoT Applications},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {202},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778078},
doi = {10.23919/VLSIC.2019.8778078},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/MatsubaraNKMSIA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/MehtaLYMS19,
author = {Nandish Mehta and
Sen Lin and
Bozhi Yin and
Sajjad Moazeni and
Vladimir Stojanovic},
title = {A Laser-forwarded Coherent 10Gb/s {BPSK} Transceiver using Monolithic
Microring Resonators in 45nm {SOI} {CMOS}},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {192},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777962},
doi = {10.23919/VLSIC.2019.8777962},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/MehtaLYMS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/MengLZYTK19,
author = {Xiaodong Meng and
Xing Li and
Xiaopeng Zhong and
Yuan Yao and
Chi{-}Ying Tsui and
Wing{-}Hung Ki},
title = {A 2.2{\(\mu\)}W 600kHz Frequency-Locked Relaxation Oscillator with
0.046{\%}/V Voltage and 48.69ppm/{\textdegree}C Temperature Stability
for IoT Sensor Node Applications},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {44},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778065},
doi = {10.23919/VLSIC.2019.8778065},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/MengLZYTK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/MoodyDBLLDGTBGC19,
author = {Jesse Moody and
Anjana Dissanayake and
Henry L. Bishop and
Ruochen Lu and
Ningxi Liu and
Divya Duvvuri and
Anming Gao and
Daniel S. Truesdell and
N. Scott Barker and
Songbin Gong and
Benton H. Calhoun and
Steven M. Bowers},
title = {A -106dBm 33nW Bit-Level Duty-Cycled Tuned {RF} Wake-up Receiver},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {86},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777956},
doi = {10.23919/VLSIC.2019.8777956},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/MoodyDBLLDGTBGC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/NurmetovFMDKB19,
author = {Umidjon Nurmetov and
Tobias Fritz and
Ernst M{\"{u}}llner and
Christopher M. Dougherty and
Franz Kreupl and
Ralf Brederlow},
title = {A {CMOS} Temperature Stabilized 2-Dimensional Mechanical Stress Sensor
with 11-bit Resolution},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {64},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778132},
doi = {10.23919/VLSIC.2019.8778132},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/NurmetovFMDKB19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/OConnorMMMBRSFF19,
author = {Patrick O'Connor and
Casey Meekhof and
Chad McBride and
Christopher Mei and
Cyrus S. Bamji and
Dave Rohn and
Hakon Strande and
Justin Forrester and
Mike Fenton and
Ryan Haraden and
Tolga Ozguner and
Travis Perry},
title = {Custom Silicon and Sensors Developed for a 2nd Generation Mixed Reality
User Interface},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {186},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778092},
doi = {10.23919/VLSIC.2019.8778092},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/OConnorMMMBRSFF19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/OkumuraYHN19,
author = {Shunsuke Okumura and
Makoto Yabuuchi and
Kenichiro Hijioka and
Koichi Nose},
title = {A Ternary Based Bit Scalable, 8.80 {TOPS/W} {CNN} accelerator with
Many-core Processing-in-memory Architecture with 896K synapses/mm\({}^{\mbox{2}}\)},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {248},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778187},
doi = {10.23919/VLSIC.2019.8778187},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/OkumuraYHN19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/PalPFGTRXZAWBCC19,
author = {Subhankar Pal and
Dong{-}Hyeon Park and
Siying Feng and
Paul Gao and
Jielun Tan and
Austin Rovinski and
Shaolin Xie and
Chun Zhao and
Aporva Amarnath and
Timothy Wesley and
Jonathan Beaumont and
Kuan{-}Yu Chen and
Chaitali Chakrabarti and
Michael B. Taylor and
Trevor N. Mudge and
David T. Blaauw and
Hun{-}Seok Kim and
Ronald G. Dreslinski},
title = {A 7.3 {M} Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator
using Memory Reconfiguration in 40 nm},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {150},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778147},
doi = {10.23919/VLSIC.2019.8778147},
timestamp = {Mon, 20 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/PalPFGTRXZAWBCC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ParkJLKKK19,
author = {Jungwoon Park and
Junyoung Jang and
Geunhaeng Lee and
Hyunmin Koh and
Changhwan Kim and
Tae Wook Kim},
title = {A Time Domain Artificial Intelligence Radar for Hand Gesture Recognition
Using 33-GHz Direct Sampling},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {24},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777995},
doi = {10.23919/VLSIC.2019.8777995},
timestamp = {Tue, 02 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ParkJLKKK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ParkJPPCC19,
author = {Injun Park and
Woojin Jo and
Chanmin Park and
Byungchoul Park and
Jimin Cheon and
Youngcheol Chae},
title = {A 640{\texttimes}640 Fully Dynamic {CMOS} Image Sensor for Always-On
Object Recognition},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {214},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778169},
doi = {10.23919/VLSIC.2019.8778169},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ParkJPPCC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ParkLCLHCJ19,
author = {Kwanseo Park and
Kwangho Lee and
Sung{-}Yong Cho and
Jinhyung Lee and
Jeongho Hwang and
Min{-}Seong Choo and
Deog{-}Kyoon Jeong},
title = {A 4-to-20Gb/s 1.87pJ/b Referenceless Digital {CDR} With Unlimited
Frequency Detection Capability in 65nm {CMOS}},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {194},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778157},
doi = {10.23919/VLSIC.2019.8778157},
timestamp = {Mon, 15 Jun 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ParkLCLHCJ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ParkMSJK19,
author = {Inho Park and
Junyoung Maeng and
Minseob Shim and
Junwon Jeong and
Chulwoo Kim},
title = {A Bidirectional High-Voltage Dual-Input Buck Converter for Triboelectric
Energy-Harvesting Interface Achieving 70.72{\%} End-to-End Efficiency},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {326},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778018},
doi = {10.23919/VLSIC.2019.8778018},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ParkMSJK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ParkPCC19,
author = {Byungchoul Park and
Injun Park and
Woojun Choi and
Youngcheol Chae},
title = {A 64{\texttimes}64 APD-Based ToF Image Sensor with Background Light
Suppression up to 200 klx Using In-Pixel Auto-Zeroing and Chopping},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {256},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778015},
doi = {10.23919/VLSIC.2019.8778015},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ParkPCC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/PfaffMGCWPARAHL19,
author = {Dirk Pfaff and
Shahaboddin Moazzeni and
Leisheng Gao and
Mei{-}Chen Chuang and
Xin{-}Jie Wang and
Chai Palusa and
Robert Abbott and
Rolando Ramirez and
Maher Amer and
Ming{-}Chieh Huang and
Chih{-}Chang Lin and
Fred Kuo and
Wei{-}Li Chen and
Tae Young Goh and
Kenny Hsieh},
title = {A 56Gb/s Long Reach Fully Adaptive Wireline {PAM-4} Transceiver in
7nm FinFET},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {270},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778051},
doi = {10.23919/VLSIC.2019.8778051},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/PfaffMGCWPARAHL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/RajFAMHBCGEC19,
author = {Mayank Raj and
Yohan Frans and
Sai Lalith Chaitanya Ambatipudi and
David Mahashin and
Peter De Heyn and
Sadhishkumar Balakrishnan and
Joris Van Campenhout and
Jimmy Grayson and
Marc Epitaux and
Ken Chang},
title = {A 50Gb/s Hybrid Integrated Si-Photonic Optical Link in 16nm FinFET},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {190},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778047},
doi = {10.23919/VLSIC.2019.8778047},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/RajFAMHBCGEC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/RovinskiZAGXTDA19,
author = {Austin Rovinski and
Chun Zhao and
Khalid Al{-}Hawaj and
Paul Gao and
Shaolin Xie and
Christopher Torng and
Scott Davidson and
Aporva Amarnath and
Luis Vega and
Bandhav Veluri and
Anuj Rao and
Tutu Ajayi and
Julian Puscar and
Steve Dai and
Ritchie Zhao and
Dustin Richmond and
Zhiru Zhang and
Ian Galton and
Christopher Batten and
Michael B. Taylor and
Ronald G. Dreslinski},
title = {A 1.4 GHz 695 Giga Risc-V Inst/s 496-Core Manycore Processor With
Mesh On-Chip Network and an All-Digital Synthesized {PLL} in 16nm
{CMOS}},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {30},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778031},
doi = {10.23919/VLSIC.2019.8778031},
timestamp = {Tue, 12 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/RovinskiZAGXTDA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/SatpathySKGGAKA19,
author = {Sudhir Satpathy and
Vikram B. Suresh and
Raghavan Kumar and
Vinodh Gopal and
James Guilford and
Mark A. Anders and
Himanshu Kaul and
Amit Agarwal and
Steven Hsu and
Ram Krishnamurthy and
Vivek De and
Sanu Mathew},
title = {A 1.4GHz 20.5Gbps {GZIP} decompression accelerator in 14nm {CMOS}
featuring dual-path out-of-order speculative Huffman decoder and multi-write
enabled register file array},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {238},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777934},
doi = {10.23919/VLSIC.2019.8777934},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/SatpathySKGGAKA19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/SebastianBDGJJK19,
author = {Abu Sebastian and
Irem Boybat and
Martino Dazzi and
Iason Giannopoulos and
Vara Prasad Jonnalagadda and
Vinay Joshi and
Geethan Karunaratne and
Benedikt Kersting and
Riduan Khaddam{-}Aljameh and
S. R. Nandakumar and
Anastasios Petropoulos and
Christophe Piveteau and
Theodore Antonakopoulos and
Bipin Rajendran and
Manuel Le Gallo and
Evangelos Eleftheriou},
title = {Computational memory-based inference and training of deep neural networks},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {168},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778178},
doi = {10.23919/VLSIC.2019.8778178},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/SebastianBDGJJK19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/SeoKCR19,
author = {Min{-}Jae Seo and
Ye{-}Dam Kim and
Jae{-}Hyun Chung and
Seung{-}Tak Ryu},
title = {A 40nm {CMOS} 12b 200MS/s Single-amplifier Dual-residue Pipelined-SAR
{ADC}},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {72},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778005},
doi = {10.23919/VLSIC.2019.8778005},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/SeoKCR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/SeolSBJ19,
author = {Ji{-}Hwan Seol and
Dennis Sylvester and
David T. Blaauw and
Tae{-}Kwang Jang},
title = {A Reference Oversampling Digital Phase-Locked Loop with -240 dB {FOM}
and -80 dBc Reference Spur},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {160},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778010},
doi = {10.23919/VLSIC.2019.8778010},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/SeolSBJ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ShanFXYS19,
author = {Weiwei Shan and
Ao Fan and
Jiaming Xu and
Jun Yang and
Mingoo Seok},
title = {A 923 Gbps/W, 113-Cycle, 2-Sbox Energy-efficient {AES} Accelerator
in 28nm {CMOS}},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {236},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778189},
doi = {10.23919/VLSIC.2019.8778189},
timestamp = {Tue, 03 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ShanFXYS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ShenMLTLS19,
author = {Linxiao Shen and
Abhishek Mukherjee and
Shaolan Li and
Xiyuan Tang and
Nanshu Lu and
Nan Sun},
title = {A 0.6-V Tail-Less Inverter Stacking Amplifier with 0.96 {PEF}},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {144},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778011},
doi = {10.23919/VLSIC.2019.8778011},
timestamp = {Mon, 25 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ShenMLTLS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ShiahCCLPCCJCHT19,
author = {Chun Shiah and
C. N. Chang and
Richard Crisp and
C. P. Lin and
C. N. Pan and
C. P. Chuang and
H. L. Chen and
S. H. Jheng and
T. F. Chang and
W. J. Huang and
K. C. Ting and
Rick Dai and
W. M. Huang and
Bor{-}Doou Rong and
Nicky Lu},
title = {A 4.8GB/s 256Mb(x16) Reduced-Pin-Count {DRAM} and Controller Architecture
{(RPCA)} to Reduce Form-Factor {\&} Cost for IOT/Wearable/TCON/Video/AI-Edge
Systems},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {116},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778049},
doi = {10.23919/VLSIC.2019.8778049},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ShiahCCLPCCJCHT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/SuC19,
author = {Shiyu Su and
Mike Shuo{-}Wei Chen},
title = {A 1-5GHz Direct-Digital {RF} Modulator with an Embedded Time-Approximation
Filter Achieving -43dB {EVM} at 1024 {QAM}},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {20},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778115},
doi = {10.23919/VLSIC.2019.8778115},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/SuC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/SureshSKAK0HKDM19,
author = {Vikram B. Suresh and
Sudhir Satpathy and
Raghavan Kumar and
Mark A. Anders and
Himanshu Kaul and
Amit Agarwal and
Steven Hsu and
Ram Krishnamurthy and
Vivek De and
Sanu Mathew},
title = {A 250Mv, 0.063J/Ghash Bitcoin Mining Engine in 14nm {CMOS} Featuring
Dual-Vcc Sha256 Datapath and 3-Phase Latch Based Clocking},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {32},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777966},
doi = {10.23919/VLSIC.2019.8777966},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/SureshSKAK0HKDM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/TajalliBCCFGGGH19,
author = {Armin Tajalli and
Mani Bastani Parizi and
Dario Albino Carnelli and
Chen Cao and
John Fox and
Kiarash Gharibdoust and
Davide Gorret and
Amit Gupta and
Christopher Hall and
Ahmed Hassanin and
Klaas L. Hofstra and
Brian Holden and
Ali Hormati and
John Keay and
Yohann Mogentale and
G. Paul and
Victor Perrin and
John Phillips and
Sumathi Raparthy and
Amin Shokrollahi and
David Stauffer and
Richard Simpson and
Andrew Stewart and
Giuseppe Surace and
Omid Talebi Amiri and
Emanuele Truffa and
Anton Tschank and
Roger Ulrich and
Christoph Walter and
Anant Singh},
title = {A 1.02pJ/b 417Gb/s/mm {USR} Link in 16nm FinFET},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {92},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778172},
doi = {10.23919/VLSIC.2019.8778172},
timestamp = {Fri, 07 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/TajalliBCCFGGGH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/TakkenFWMJZ19,
author = {Todd Takken and
Andrew Ferencz and
Chung{-}Shiang Wu and
Liam McAuliffe and
Tianyu Jia and
Xin Zhang},
title = {A 48 {V} Input 0.75 {V} Output {DC-DC} Converter Power Block for {HPC}
Systems and Datacenters (invited paper)},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {168},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778088},
doi = {10.23919/VLSIC.2019.8778088},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/TakkenFWMJZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/TanakaTTSNTSIKY19,
author = {Takahisa Tanaka and
K. Tabuchi and
Kohei Tatehora and
Yohsuke Shiiki and
S. Nakagawa and
Tsunaki Takahashi and
R. Shimizu and
Hiroki Ishikuro and
Tadahiro Kuroda and
T. Yanagida and
Ken Uchida},
title = {Low-Power and ppm-Level Detection of Gas Molecules by Integrated Metal
Nanosheets},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {158},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778016},
doi = {10.23919/VLSIC.2019.8778016},
timestamp = {Wed, 22 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/TanakaTTSNTSIKY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/TangKSYSS19,
author = {Xiyuan Tang and
Begum Kasap and
Linxiao Shen and
Xiangxing Yang and
Wei Shi and
Nan Sun},
title = {An Energy-Efficient Comparator with Dynamic Floating Inverter Pre-Amplifier},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {140},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777942},
doi = {10.23919/VLSIC.2019.8777942},
timestamp = {Mon, 25 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/TangKSYSS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/TangWYHCXKWHLLH19,
author = {Kea{-}Tiong Tang and
Wei{-}Chen Wei and
Zuo{-}Wei Yeh and
Tzu{-}Hsiang Hsu and
Yen{-}Cheng Chiu and
Cheng{-}Xin Xue and
Yu{-}Chun Kuo and
Tai{-}Hsing Wen and
Mon{-}Shu Ho and
Chung{-}Chuan Lo and
Ren{-}Shuo Liu and
Chih{-}Cheng Hsieh and
Meng{-}Fan Chang},
title = {Considerations Of Integrating Computing-In-Memory And Processing-In-Sensor
Into Convolutional Neural Network Accelerators For Low-Power Edge
Devices},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {166},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778074},
doi = {10.23919/VLSIC.2019.8778074},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/TangWYHCXKWHLLH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/TaoCZ19,
author = {Yaoyu Tao and
Sung{-}Gun Cho and
Zhengya Zhang},
title = {A 3.25Gb/s, 13.2pJ/b, 0.64mm\({}^{\mbox{2}}\) Configurable Successive-Cancellation
List Polar Decoder using Split-Tree Architecture in 40nm {CMOS}},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {240},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778009},
doi = {10.23919/VLSIC.2019.8778009},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/TaoCZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/TaoH19,
author = {Jingcheng Tao and
Chun{-}Huat Heng},
title = {A 2.2-GHz 3.2-mW DTC-free Sampling {\(\Delta\)}{\(\Sigma\)} Fractional-N
{PLL} with -110 dBc/Hz In-band phase noise and -246dB FoM and -83dBc
Reference Spur},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {162},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778000},
doi = {10.23919/VLSIC.2019.8778000},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/TaoH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/TheerthamKBP19,
author = {Raviteja Theertham and
Prasanth Koottala and
Sujith Billa and
Shanthi Pavan},
title = {A 24mW Chopped {CTDSM} Achieving 103.5dB {SNDR} and 107.5dB {DR} in
a 250kHz Bandwidth},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {226},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778026},
doi = {10.23919/VLSIC.2019.8778026},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/TheerthamKBP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/WangSZWD19,
author = {Hechen Wang and
Zhan Su and
Haoyi Zhao and
Yanjie Wang and
Fa Foster Dai},
title = {A 3.8 mW Sub-Sampling Direct RF-to-Digital Converter for Polar Receiver
Achieving 1.94 Gb/s Data Rate with 1024-APSK Modulation},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {82},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778052},
doi = {10.23919/VLSIC.2019.8778052},
timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/WangSZWD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/WangZZY19,
author = {Can Wang and
Guang Zhu and
Zhao Zhang and
C. Patrick Yue},
title = {A 52-Gb/s Sub-1pJ/bit {PAM4} Receiver in 40-nm {CMOS} for Low-Power
Interconnects},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {274},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778159},
doi = {10.23919/VLSIC.2019.8778159},
timestamp = {Fri, 29 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/WangZZY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/Warren19,
author = {Mial E. Warren},
title = {Automotive {LIDAR} Technology},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {254},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777993},
doi = {10.23919/VLSIC.2019.8777993},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/Warren19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/WeiLM19,
author = {Kang Wei and
Bumkil Lee and
Dongsheng Brian Ma},
title = {A 10-MHz 14.3W/mm\({}^{\mbox{2}}\) {DAB} Hysteretic Control Power
Converter Achieving 2.5W/247ns Full Load Power Flipping and above
80{\%} Efficiency in 99.9{\%} Power Range for 5G IoTs},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {172},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778192},
doi = {10.23919/VLSIC.2019.8778192},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/WeiLM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/WengWHWW19,
author = {Chan{-}Hsiang Weng and
Tzu{-}An Wei and
Hung{-}Yi Hsieh and
Su{-}Hao Wu and
Ting{-}Yang Wang},
title = {A 71. 4dB {SNDR} 30MHz {BW} Continuous-Time Delta-sigma Modulator
Using a Time-Interleaved Noise-Shaping Quantizer in 12-nm {CMOS}},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {228},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777949},
doi = {10.23919/VLSIC.2019.8777949},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/WengWHWW19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/WhatmoughLDHXGP19,
author = {Paul N. Whatmough and
Sae Kyu Lee and
Marco Donato and
Hsea{-}Ching Hsueh and
Sam Likun Xi and
Udit Gupta and
Lillian Pentecost and
Glenn G. Ko and
David M. Brooks and
Gu{-}Yeon Wei},
title = {A 16nm 25mm\({}^{\mbox{2}}\) SoC with a 54.5x Flexibility-Efficiency
Range from Dual-Core Arm Cortex-A53 to eFPGA and Cache-Coherent Accelerators},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {34},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778002},
doi = {10.23919/VLSIC.2019.8778002},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/WhatmoughLDHXGP19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/WiserSSKKYAPBPC19,
author = {Bob Wiser and
Kannan A. Sankaragomathi and
Justin Schauer and
Sean Korhummel and
Pouya Kavousian and
Daniel J. Yeager and
Nivi Arumugam and
Nate Pletcher and
David Barkin and
Reed Parker and
Lori Callaghan and
Richard C. Ruby and
Brian Otis},
title = {A 1.53 mm\({}^{\mbox{3}}\) crystal-less standards-compliant Bluetooth
Low Energy module for volume constrained wireless sensors},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {84},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777950},
doi = {10.23919/VLSIC.2019.8777950},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/WiserSSKKYAPBPC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/YanKM19,
author = {Dong Yan and
Xugang Ke and
Dongsheng Brian Ma},
title = {A Two-Phase 2MHz {DSD} GaN Power Converter with Master-Slave AO\({}^{\mbox{2}}\)T
Control for Direct 48V/1V {DC-DC} Conversion},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {170},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778017},
doi = {10.23919/VLSIC.2019.8778017},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/YanKM19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/YangXCBZWHH19,
author = {Xiaolin Yang and
Jiawei Xu and
Hosung Chun and
Marco Ballini and
Menglian Zhao and
Xiaobo Wu and
Chris Van Hoof and
Nick Van Helleputte},
title = {A 108dB {DR} Hybrid-CTDT Direct-Digitalization {\(\Delta\)}{\(\Sigma\)}-{\(\Sigma\)}M
Front-End with 720mVpp Input Range and {\textgreater}300mV Offset
Removal for Wearable Bio-Signal Recording},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {296},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778185},
doi = {10.23919/VLSIC.2019.8778185},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/YangXCBZWHH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/YingCTLH19,
author = {Da Ying and
Ping{-}Wei Chen and
Chi Tseng and
Yu{-}Hwa Lo and
Drew A. Hall},
title = {A Sub-pA Current Sensing Front-End for Transient Induced Molecular
Spectroscopy},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {316},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777980},
doi = {10.23919/VLSIC.2019.8777980},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/YingCTLH19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ZhaNL19,
author = {Yue Zha and
Etienne Nowak and
Jing Li},
title = {Liquid Silicon: {A} Nonvolatile Fully Programmable Processing-In-Memory
Processor with Monolithically Integrated ReRAM for Big Data/Machine
Learning Applications},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {206},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778064},
doi = {10.23919/VLSIC.2019.8778064},
timestamp = {Sun, 25 Oct 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ZhaNL19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ZhangLLSKZ19,
author = {Jie{-}Fang Zhang and
Ching{-}En Lee and
Chester Liu and
Yakun Sophia Shao and
Stephen W. Keckler and
Zhengya Zhang},
title = {{SNAP:} {A} 1.67 - 21.55TOPS/W Sparse Neural Acceleration Processor
for Unstructured Sparse Deep Neural Network Inference in 16nm {CMOS}},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {306},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778193},
doi = {10.23919/VLSIC.2019.8778193},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/ZhangLLSKZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ZhangNHLWSO19,
author = {Haosheng Zhang and
Aravind Tharayil Narayanan and
Hans Herdian and
Bangan Liu and
Yun Wang and
Atsushi Shirane and
Kenichi Okada},
title = {0.2mW 70Fsrms-Jitter Injection-Locked {PLL} Using De-Sensitized SSPD-Based
Injecting-Time Self-Alignment Achieving -270dB FoM and -66dBc Reference
Spur},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {38},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778059},
doi = {10.23919/VLSIC.2019.8778059},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ZhangNHLWSO19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ZhangZY19,
author = {Zhao Zhang and
Guang Zhu and
C. Patrick Yue},
title = {A 0.25-0.4V, Sub-0.11mW/GHz, 0.15-1.6GHz {PLL} Using an Offset Dual-Path
Loop Architecture with Dynamic Charge Pumps},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {158},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778061},
doi = {10.23919/VLSIC.2019.8778061},
timestamp = {Mon, 05 Aug 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ZhangZY19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ZhuBOC19,
author = {Yukun Zhu and
Pranith R. Byreddy and
Kenneth K. O and
Wooyeol Choi},
title = {426-GHz Imaging Pixel Integrating a Transmitter and a Coherent Receiver
with an Area of 380{\texttimes}47{\(\mu\)}m\({}^{\mbox{2}}\) in 65-nm
{CMOS}},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {18},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778039},
doi = {10.23919/VLSIC.2019.8778039},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ZhuBOC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ZimmerVSCFJKKPR19,
author = {Brian Zimmer and
Rangharajan Venkatesan and
Yakun Sophia Shao and
Jason Clemons and
Matthew Fojtik and
Nan Jiang and
Ben Keller and
Alicia Klinefelter and
Nathaniel Ross Pinckney and
Priyanka Raina and
Stephen G. Tell and
Yanqing Zhang and
William J. Dally and
Joel S. Emer and
C. Thomas Gray and
Stephen W. Keckler and
Brucek Khailany},
title = {A 0.11 pJ/Op, 0.32-128 TOPS, Scalable Multi-Chip-Module-based Deep
Neural Network Accelerator with Ground-Reference Signaling in 16nm},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {300},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8778056},
doi = {10.23919/VLSIC.2019.8778056},
timestamp = {Thu, 23 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsic/ZimmerVSCFJKKPR19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsic/ZulianiCC19,
author = {Paola Zuliani and
A. Conte and
P. Cappelletti},
title = {The {PCM} way for embedded Non Volatile Memories applications},
booktitle = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
pages = {192},
publisher = {{IEEE}},
year = {2019},
url = {https://doi.org/10.23919/VLSIC.2019.8777957},
doi = {10.23919/VLSIC.2019.8777957},
timestamp = {Sun, 13 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/ZulianiCC19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vlsic/2019,
title = {2019 Symposium on {VLSI} Circuits, Kyoto, Japan, June 9-14, 2019},
publisher = {{IEEE}},
year = {2019},
url = {https://ieeexplore.ieee.org/xpl/conhome/8766307/proceeding},
isbn = {978-4-86348-720-8},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsic/2019.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
retrieved on 2024-04-19 08:16 CEST from data curated by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
