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@article{DBLP:journals/tcad/0001MTA16, author = {Anup Das and Geoff V. Merrett and Mirco Tribastone and Bashir M. Al{-}Hashimi}, title = {Workload Change Point Detection for Runtime Thermal Management of Embedded Systems}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {8}, pages = {1358--1371}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2504875}, doi = {10.1109/TCAD.2015.2504875}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/0001MTA16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/AgrawalCE16, author = {Mukesh Agrawal and Krishnendu Chakrabarty and Bill Eklow}, title = {A Distributed, Reconfigurable, and Reusable {BIST} Infrastructure for Test and Diagnosis of 3-D-Stacked ICs}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {2}, pages = {309--322}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2459044}, doi = {10.1109/TCAD.2015.2459044}, timestamp = {Thu, 09 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/AgrawalCE16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/AhadiR16, author = {Majid Ahadi and Sourajeet Roy}, title = {Sparse Linear Regression {(SPLINER)} Approach for Efficient Multidimensional Uncertainty Quantification of High-Speed Circuits}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {10}, pages = {1640--1652}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2527711}, doi = {10.1109/TCAD.2016.2527711}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/AhadiR16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/AhmadyanV16, author = {Seyed Nematollah Adel Ahmadyan and Shobha Vasudevan}, title = {Automated Transient Input Stimuli Generation for Analog Circuits}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {5}, pages = {858--871}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2488482}, doi = {10.1109/TCAD.2015.2488482}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/AhmadyanV16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/AhnKPK16, author = {Seyong Ahn and Minseok Kang and Marios C. Papaefthymiou and Taewhan Kim}, title = {Design Methodology for Synthesizing Resonant Clock Networks in the Presence of Dynamic Voltage/Frequency Scaling}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {12}, pages = {2068--2081}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2543022}, doi = {10.1109/TCAD.2016.2543022}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/AhnKPK16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/AinCD16, author = {Antara Ain and Antonio Anastasio Bruto da Costa and Pallab Dasgupta}, title = {Feature Indented Assertions for Analog and Mixed-Signal Validation}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {11}, pages = {1928--1941}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2525798}, doi = {10.1109/TCAD.2016.2525798}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/AinCD16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/AlistarPM16, author = {Mirela Alistar and Paul Pop and Jan Madsen}, title = {Synthesis of Application-Specific Fault-Tolerant Digital Microfluidic Biochip Architectures}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {5}, pages = {764--777}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2528498}, doi = {10.1109/TCAD.2016.2528498}, timestamp = {Thu, 14 Oct 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/AlistarPM16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/AmaruGM16, author = {Luca Gaetano Amar{\`{u}} and Pierre{-}Emmanuel Gaillardon and Giovanni De Micheli}, title = {Majority-Inverter Graph: {A} New Paradigm for Logic Optimization}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {5}, pages = {806--819}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2488484}, doi = {10.1109/TCAD.2015.2488484}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/AmaruGM16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/AmouriHT16, author = {Abdulazim Amouri and Jochen Hepp and Mehdi Baradaran Tahoori}, title = {Built-In Self-Heating Thermal Testing of FPGAs}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {9}, pages = {1546--1556}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2512905}, doi = {10.1109/TCAD.2015.2512905}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/AmouriHT16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/AnYH16, author = {Hyung{-}Chan An and Hoeseok Yang and Soonhoi Ha}, title = {A Formal Approach to Power Optimization in CPSs With Delay-Workload Dependence Awareness}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {5}, pages = {750--763}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2527702}, doi = {10.1109/TCAD.2016.2527702}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/AnYH16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ArslanO16, author = {Baris Arslan and Alex Orailoglu}, title = {Power-Aware Delay Test Quality Optimization for Multiple Frequency Domains}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {1}, pages = {141--154}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2448689}, doi = {10.1109/TCAD.2015.2448689}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ArslanO16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ArslanO16a, author = {Baris Arslan and Alex Orailoglu}, title = {Aggressive Test Cost Reductions Through Continuous Test Effectiveness Assessment}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {12}, pages = {2093--2103}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2535902}, doi = {10.1109/TCAD.2016.2535902}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ArslanO16a.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/BalabanovLJ16, author = {Valeriy Balabanov and Shuo{-}Ren Lin and Jie{-}Hong R. Jiang}, title = {Flexibility and Optimization of {QBF} Skolem-Herbrand Certificates}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {9}, pages = {1557--1568}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2512906}, doi = {10.1109/TCAD.2015.2512906}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/BalabanovLJ16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/BalefKAP16, author = {Hadi Ahmadi Balef and Mehdi Kamal and Ali Afzali{-}Kusha and Massoud Pedram}, title = {All-Region Statistical Model for Delay Variation Based on Log-Skew-Normal Distribution}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {9}, pages = {1503--1508}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2511148}, doi = {10.1109/TCAD.2015.2511148}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/BalefKAP16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/Balsamo0WBAMB16, author = {Domenico Balsamo and Anup Das and Alex S. Weddell and Davide Brunelli and Bashir M. Al{-}Hashimi and Geoff V. Merrett and Luca Benini}, title = {Graceful Performance Modulation for Power-Neutral Transient Computing Systems}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {5}, pages = {738--749}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2527713}, doi = {10.1109/TCAD.2016.2527713}, timestamp = {Mon, 03 Jan 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/Balsamo0WBAMB16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/BalsamoWDABAMB16, author = {Domenico Balsamo and Alex S. Weddell and Anup Das and Alberto Rodriguez Arreola and Davide Brunelli and Bashir M. Al{-}Hashimi and Geoff V. Merrett and Luca Benini}, title = {Hibernus++: {A} Self-Calibrating and Adaptive System for Transiently-Powered Embedded Devices}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {12}, pages = {1968--1980}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2547919}, doi = {10.1109/TCAD.2016.2547919}, timestamp = {Sun, 02 Oct 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/BalsamoWDABAMB16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/BaoFS16, author = {Chongxi Bao and Domenic Forte and Ankur Srivastava}, title = {On Reverse Engineering-Based Hardware Trojan Detection}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {1}, pages = {49--57}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2488495}, doi = {10.1109/TCAD.2015.2488495}, timestamp = {Wed, 07 Dec 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/BaoFS16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/BarrioCH16, author = {Alberto A. Del Barrio and Jason Cong and Rom{\'{a}}n Hermida}, title = {A Distributed Clustered Architecture to Tackle Delay Variations in Datapath Synthesis}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {3}, pages = {419--432}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2474362}, doi = {10.1109/TCAD.2015.2474362}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/BarrioCH16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/BasakB16, author = {Abhishek Basak and Swarup Bhunia}, title = {P-Val: Antifuse-Based Package-Level Defense Against Counterfeit ICs}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {7}, pages = {1067--1078}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2501311}, doi = {10.1109/TCAD.2015.2501311}, timestamp = {Tue, 07 May 2024 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/BasakB16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/BeneventiBVB16, author = {Francesco Beneventi and Andrea Bartolini and Pascal Vivet and Luca Benini}, title = {Thermal Analysis and Interpolation Techniques for a Logic + WideIO Stacked {DRAM} Test Chip}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {4}, pages = {623--636}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2474382}, doi = {10.1109/TCAD.2015.2474382}, timestamp = {Tue, 07 May 2024 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/BeneventiBVB16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/BuccellaSZMISK16, author = {Pietro Buccella and Camillo Stefanucci and Hao Zou and Yasser Moursy and Ramy Iskander and Jean{-}Michel Sallese and Maher Kayal}, title = {Methodology for 3-D Substrate Network Extraction for {SPICE} Simulation of Parasitic Currents in Smart Power ICs}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {9}, pages = {1489--1502}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2513008}, doi = {10.1109/TCAD.2015.2513008}, timestamp = {Tue, 17 Aug 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/BuccellaSZMISK16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/BurceaHG16, author = {Florin Burcea and Husni M. Habal and Helmut E. Graeb}, title = {A New Chessboard Placement and Sizing Method for Capacitors in a Charge-Scaling {DAC} by Worst-Case Analysis of Nonlinearity}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {9}, pages = {1397--1410}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2511146}, doi = {10.1109/TCAD.2015.2511146}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/BurceaHG16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/CaiJGPM16, author = {Ermao Cai and Da{-}Cheng Juan and Siddharth Garg and Jinpyo Park and Diana Marculescu}, title = {Learning-Based Power/Performance Optimization for Many-Core Systems With Extended-Range Voltage/Frequency Scaling}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {8}, pages = {1318--1331}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2504330}, doi = {10.1109/TCAD.2015.2504330}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/CaiJGPM16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/CamposMNT16, author = {Caio Araujo T. Campos and Abner Luis Panho Marciano and Omar P. Vilela Neto and Frank Sill Torres}, title = {{USE:} {A} Universal, Scalable, and Efficient Clocking Scheme for {QCA}}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {3}, pages = {513--517}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2471996}, doi = {10.1109/TCAD.2015.2471996}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/CamposMNT16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ChenNCGLRCHC16, author = {Ying Chen and Tan Nguyen and Yao Chen and Swathi T. Gurumani and Yun Liang and Kyle Rupnow and Jason Cong and Wen{-}mei W. Hwu and Deming Chen}, title = {{FCUDA-HB:} Hierarchical and Scalable Bus Architecture Generation on FPGAs With the {FCUDA} Flow}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {12}, pages = {2032--2045}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2552821}, doi = {10.1109/TCAD.2016.2552821}, timestamp = {Tue, 19 Sep 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ChenNCGLRCHC16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ChenTHKS16, author = {Hai{-}Bao Chen and Sheldon X.{-}D. Tan and Xin Huang and Taeyoung Kim and Valeriy Sukharev}, title = {Analytical Modeling and Characterization of Electromigration Effects for Multibranch Interconnect Trees}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {11}, pages = {1811--1824}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2523898}, doi = {10.1109/TCAD.2016.2523898}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ChenTHKS16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ChenWLWLLY16, author = {Xiaoming Chen and Lin Wang and Boxun Li and Yu Wang and Xin Li and Yongpan Liu and Huazhong Yang}, title = {Modeling Random Telegraph Noise as a Randomness Source and its Application in True Random Number Generation}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {9}, pages = {1435--1448}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2511074}, doi = {10.1109/TCAD.2015.2511074}, timestamp = {Thu, 22 Apr 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ChenWLWLLY16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ChiLX16, author = {Ping Chi and Wang{-}Chien Lee and Yuan Xie}, title = {Adapting B\({}^{\mbox{+}}\) -Tree for Emerging Nonvolatile Memory-Based Main Memory}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {9}, pages = {1461--1474}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2512899}, doi = {10.1109/TCAD.2015.2512899}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ChiLX16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ChiangLJC16, author = {Hui{-}Ju Katherine Chiang and Chi{-}Yuan Liu and Jie{-}Hong R. Jiang and Yao{-}Wen Chang}, title = {Simultaneous {EUV} Flare Variation Minimization and {CMP} Control by Coupling-Aware Dummification}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {4}, pages = {598--610}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2488492}, doi = {10.1109/TCAD.2015.2488492}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ChiangLJC16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/CiccazzoPL16, author = {Angelo Ciccazzo and Gianni Di Pillo and Vittorio Latorre}, title = {A {SVM} Surrogate Model-Based Method for Parametric Yield Optimization}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {7}, pages = {1224--1228}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2501307}, doi = {10.1109/TCAD.2015.2501307}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/CiccazzoPL16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/CongLXZ16, author = {Jason Cong and Peng Li and Bingjun Xiao and Peng Zhang}, title = {An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {3}, pages = {407--418}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2488491}, doi = {10.1109/TCAD.2015.2488491}, timestamp = {Sun, 02 Oct 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/CongLXZ16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/DaloukasETS16, author = {Konstantis Daloukas and Nestor E. Evmorfopoulos and Panagiota E. Tsompanopoulou and George I. Stamoulis}, title = {Parallel Fast Transform-Based Preconditioners for Large-Scale Power Grid Analysis on Graphics Processing Units (GPUs)}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {10}, pages = {1653--1666}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2523933}, doi = {10.1109/TCAD.2016.2523933}, timestamp = {Thu, 07 Jan 2021 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/DaloukasETS16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/DingCC16, author = {Jiatao Ding and Jiajia Chen and Chip{-}Hong Chang}, title = {A New Paradigm of Common Subexpression Elimination by Unification of Addition and Subtraction}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {10}, pages = {1605--1617}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2527700}, doi = {10.1109/TCAD.2016.2527700}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/DingCC16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/DongOYLG16, author = {Mianxiong Dong and Kaoru Ota and Laurence T. Yang and Anfeng Liu and Minyi Guo}, title = {{LSCD:} {A} Low-Storage Clone Detection Protocol for Cyber-Physical Systems}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {5}, pages = {712--723}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2539327}, doi = {10.1109/TCAD.2016.2539327}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/DongOYLG16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/DongZ16, author = {Xuan Dong and Lihong Zhang}, title = {Lithography-Aware Analog Layout Retargeting}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {2}, pages = {232--245}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2459041}, doi = {10.1109/TCAD.2015.2459041}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/DongZ16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/EbeidFQ16, author = {Emad Ebeid and Franco Fummi and Davide Quaglia}, title = {Erratum to "Model-Driven Design of Network Aspects of Distributed Embedded Systems"}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {5}, pages = {872}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2537681}, doi = {10.1109/TCAD.2016.2537681}, timestamp = {Sat, 09 Apr 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/EbeidFQ16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/EbrahimiABT16, author = {Mojtaba Ebrahimi and Hossein Asadi and Rajendra Bishnoi and Mehdi Baradaran Tahoori}, title = {Layout-Based Modeling and Mitigation of Multiple Event Transients}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {3}, pages = {367--379}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2459053}, doi = {10.1109/TCAD.2015.2459053}, timestamp = {Fri, 14 May 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/EbrahimiABT16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/EggersgluBSKD16, author = {Stephan Eggersgl{\"{u}}{\ss} and Kenneth Schmitz and Rene Krenz{-}Baath and Rolf Drechsler}, title = {On Optimization-Based {ATPG} and Its Application for Highly Compacted Test Sets}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {12}, pages = {2104--2117}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2552822}, doi = {10.1109/TCAD.2016.2552822}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/EggersgluBSKD16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/FongKYFSRR16, author = {Xuanyao Fong and Yusung Kim and Karthik Yogendra and Deliang Fan and Abhronil Sengupta and Anand Raghunathan and Kaushik Roy}, title = {Spin-Transfer Torque Devices for Logic and Memory: Prospects and Perspectives}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {1}, pages = {1--22}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2481793}, doi = {10.1109/TCAD.2015.2481793}, timestamp = {Mon, 28 Aug 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/FongKYFSRR16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/Gomez-PauBF16, author = {{\'{A}}lvaro G{\'{o}}mez{-}Pau and Luz Balado and Joan Figueras}, title = {Efficient Production Binning Using Octree Tessellation in the Alternate Measurements Space}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {8}, pages = {1386--1395}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2501309}, doi = {10.1109/TCAD.2015.2501309}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/Gomez-PauBF16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/GongR16, author = {Zheng Gong and Rashid Rashidzadeh}, title = {{TSV} Extracted Equivalent Circuit Model and an On-Chip Test Solution}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {4}, pages = {679--690}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2474411}, doi = {10.1109/TCAD.2015.2474411}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/GongR16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/GriggioR16, author = {Alberto Griggio and Marco Roveri}, title = {Comparing Different Variants of the ic3 Algorithm for Hardware Model Checking}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {6}, pages = {1026--1039}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2481869}, doi = {10.1109/TCAD.2015.2481869}, timestamp = {Fri, 09 Apr 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/GriggioR16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/GuSZCH16, author = {Shouzhen Gu and Edwin Hsing{-}Mean Sha and Qingfeng Zhuge and Yiran Chen and Jingtong Hu}, title = {A Time, Energy, and Area Efficient Domain Wall Memory-Based {SPM} for Embedded Systems}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {12}, pages = {2008--2017}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2547903}, doi = {10.1109/TCAD.2016.2547903}, timestamp = {Mon, 04 Jul 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/GuSZCH16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/GuoCCF16, author = {Qi Guo and Tianshi Chen and Yunji Chen and Franz Franchetti}, title = {Accelerating Architectural Simulation Via Statistical Techniques: {A} Survey}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {3}, pages = {433--446}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2481796}, doi = {10.1109/TCAD.2015.2481796}, timestamp = {Sun, 02 Oct 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/GuoCCF16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/HaJK16, author = {Keonsoo Ha and Jaeyong Jeong and Jihong Kim}, title = {An Integrated Approach for Managing Read Disturbs in High-Density {NAND} Flash Memory}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {7}, pages = {1079--1091}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2504868}, doi = {10.1109/TCAD.2015.2504868}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/HaJK16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/HameedBH16, author = {Fazal Hameed and Lars Bauer and J{\"{o}}rg Henkel}, title = {Architecting On-Chip {DRAM} Cache for Simultaneous Miss Rate and Latency Reduction}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {4}, pages = {651--664}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2488488}, doi = {10.1109/TCAD.2015.2488488}, timestamp = {Mon, 05 Feb 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/HameedBH16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/HamoudaAK16, author = {Ayman Yehia Hamouda and Mohab Anis and Karim S. Karim}, title = {Model-Based Initial Bias {(MIB):} Toward a Single-Iteration Optical Proximity Correction}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {10}, pages = {1630--1639}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2512908}, doi = {10.1109/TCAD.2015.2512908}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/HamoudaAK16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/HanCOK16, author = {Taewoo Han and Inhyuk Choi and Hyunggoy Oh and Sungho Kang}, title = {Parallelized Network-on-Chip-Reused Test Access Mechanism for Multiple Identical Cores}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {7}, pages = {1219--1223}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2481872}, doi = {10.1109/TCAD.2015.2481872}, timestamp = {Tue, 27 Feb 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/HanCOK16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/HanFBRQ16, author = {Qiushi Han and Ming Fan and Ou Bai and Shaolei Ren and Gang Quan}, title = {Temperature-Constrained Feasibility Analysis for Multicore Scheduling}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {12}, pages = {2082--2092}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2543020}, doi = {10.1109/TCAD.2016.2543020}, timestamp = {Mon, 05 Feb 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/HanFBRQ16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/Hasani16, author = {Javad Yavand Hasani}, title = {Three-Port Model of a Modern {MOS} Transistor in Millimeter Wave Band, Considering Distributed Effects}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {9}, pages = {1509--1518}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2511150}, doi = {10.1109/TCAD.2015.2511150}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/Hasani16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/HsiaoD16, author = {Yu{-}Chung Hsiao and Luca Daniel}, title = {{CAPLET:} {A} Highly Parallelized Field Solver for Capacitance Extraction Using Instantiable Basis Functions}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {3}, pages = {458--470}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2474380}, doi = {10.1109/TCAD.2015.2474380}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/HsiaoD16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/HuBC16, author = {Kai Hu and Bhargab B. Bhattacharya and Krishnendu Chakrabarty}, title = {Fault Diagnosis for Leakage and Blockage Defects in Flow-Based Microfluidic Biochips}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {7}, pages = {1179--1191}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2488489}, doi = {10.1109/TCAD.2015.2488489}, timestamp = {Mon, 03 Jan 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/HuBC16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/HuHC16, author = {Kai Hu and Tsung{-}Yi Ho and Krishnendu Chakrabarty}, title = {Wash Optimization and Analysis for Cross-Contamination Removal Under Physical Constraints in Flow-Based Microfluidic Biochips}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {4}, pages = {559--572}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2488485}, doi = {10.1109/TCAD.2015.2488485}, timestamp = {Mon, 03 Jan 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/HuHC16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/HuHZ16, author = {Shiyan Hu and Xiaobo Sharon Hu and Albert Y. Zomaya}, title = {Guest Editorial Leveraging Design Automation Techniques for Cyber-Physical System Design}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {5}, pages = {697--698}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2548179}, doi = {10.1109/TCAD.2016.2548179}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/HuHZ16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/HuangKTS16, author = {Xin Huang and Armen Kteyan and Sheldon X.{-}D. Tan and Valeriy Sukharev}, title = {Physics-Based Electromigration Models and Full-Chip Assessment for Power Grid Networks}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {11}, pages = {1848--1861}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2524540}, doi = {10.1109/TCAD.2016.2524540}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/HuangKTS16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/HuangLQWS16, author = {Min Huang and Zhaoqing Liu and Liyan Qiao and Yi Wang and Zili Shao}, title = {An Endurance-Aware Metadata Allocation Strategy for {MLC} {NAND} Flash Memory Storage Systems}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {4}, pages = {691--694}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2474394}, doi = {10.1109/TCAD.2015.2474394}, timestamp = {Mon, 28 Aug 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/HuangLQWS16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/HuangW16, author = {Hsuan{-}Ming Huang and Charles H.{-}P. Wen}, title = {Layout-Based Soft Error Rate Estimation Framework Considering Multiple Transient Faults - From Device to Circuit Level}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {4}, pages = {586--597}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2474355}, doi = {10.1109/TCAD.2015.2474355}, timestamp = {Thu, 23 Jun 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/HuangW16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/HuangW16a, author = {Tsung{-}Wei Huang and Martin D. F. Wong}, title = {UI-Timer 1.0: An Ultrafast Path-Based Timing Analysis Algorithm for {CPPR}}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {11}, pages = {1862--1875}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2524566}, doi = {10.1109/TCAD.2016.2524566}, timestamp = {Sun, 02 Oct 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/HuangW16a.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/HuangWW16, author = {Ke Huang and Jian Wen and Jim Willmore}, title = {Test-Suite-Based Analog/RF Test Time Reduction Using Canonical Correlation}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {12}, pages = {2143--2147}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2547904}, doi = {10.1109/TCAD.2016.2547904}, timestamp = {Fri, 03 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/HuangWW16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/JallepalliMPHM16, author = {Srinivas Jallepalli and Ram Mooraka and Sanjay Parihar and Earl Hunter and Elie Maalouf}, title = {Employing Scaled Sigma Sampling for Efficient Estimation of Rare Event Probabilities in the Absence of Input Domain Mapping}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {6}, pages = {943--956}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2523447}, doi = {10.1109/TCAD.2016.2523447}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/JallepalliMPHM16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/JallepalliMPHM16a, author = {Srinivas Jallepalli and Ram Mooraka and Sanjay Parihar and Earl Hunter and Elie Maalouf}, title = {Rapid Assessment of Design Sensitivity to Process Excursions via Scaled Sigma Sampling}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {6}, pages = {957--970}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2523445}, doi = {10.1109/TCAD.2016.2523445}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/JallepalliMPHM16a.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/JarndalEK16, author = {Anwar Jarndal and Riadh Essaadali and Ammar B. Kouki}, title = {A Reliable Model Parameter Extraction Method Applied to AlGaN/GaN HEMTs}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {2}, pages = {211--219}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2460461}, doi = {10.1109/TCAD.2015.2460461}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/JarndalEK16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/JiaHC16, author = {Wangkun Jia and Brian T. Helenbrook and Ming{-}C. Cheng}, title = {Fast Thermal Simulation of FinFET Circuits Based on a Multiblock Reduced-Order Model}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {7}, pages = {1114--1124}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2501305}, doi = {10.1109/TCAD.2015.2501305}, timestamp = {Mon, 26 Oct 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/JiaHC16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/JiaYLCWG16, author = {Rui Jia and Hai{-}Gang Yang and Colin Yu Lin and Rui Chen and Xin{-}Gang Wang and Zhenhong Guo}, title = {A Computationally Efficient Reconfigurable {FIR} Filter Architecture Based on Coefficient Occurrence Probability}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {8}, pages = {1297--1308}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2504922}, doi = {10.1109/TCAD.2015.2504922}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/JiaYLCWG16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/JinYZCG16, author = {Shi Jin and Fangming Ye and Zhaobo Zhang and Krishnendu Chakrabarty and Xinli Gu}, title = {Efficient Board-Level Functional Fault Diagnosis With Missing Syndromes}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {6}, pages = {985--998}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2481859}, doi = {10.1109/TCAD.2015.2481859}, timestamp = {Mon, 03 Jan 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/JinYZCG16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/Kagaris16, author = {Dimitri Kagaris}, title = {{MOTO-X:} {A} Multiple-Output Transistor-Level Synthesis {CAD} Tool}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {1}, pages = {114--127}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2448675}, doi = {10.1109/TCAD.2015.2448675}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/Kagaris16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/KangLLK16, author = {Wooheon Kang and Changwook Lee and Hyunyul Lim and Sungho Kang}, title = {A New 3-D Fuse Architecture to Improve Yield of 3-D Memories}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {10}, pages = {1763--1767}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2523444}, doi = {10.1109/TCAD.2016.2523444}, timestamp = {Tue, 27 Feb 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/KangLLK16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/KhanLWS16, author = {Muhammad Umer Khan and Shuai Li and Qixin Wang and Zili Shao}, title = {{CPS} Oriented Control Design for Networked Surveillance Robots With Multiple Physical Constraints}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {5}, pages = {778--791}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2524653}, doi = {10.1109/TCAD.2016.2524653}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/KhanLWS16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/KonigsmarkCW16, author = {Sven Tenzing Choden Konigsmark and Deming Chen and Martin D. F. Wong}, title = {PolyPUF: Physically Secure Self-Divergence}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {7}, pages = {1053--1066}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2488493}, doi = {10.1109/TCAD.2015.2488493}, timestamp = {Sun, 02 Oct 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/KonigsmarkCW16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/LaiCJ16, author = {Yi{-}Hsiang Lai and Chi{-}Chuan Chuang and Jie{-}Hong R. Jiang}, title = {Scalable Synthesis of {PCHB-WCHB} Hybrid Quasi-Delay Insensitive Circuits}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {11}, pages = {1797--1810}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2529430}, doi = {10.1109/TCAD.2016.2529430}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/LaiCJ16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/LanPC16, author = {Fan Lan and Yun Pan and Kwang{-}Ting (Tim) Cheng}, title = {An Efficient Network-on-Chip Yield Estimation Approach Based on Gibbs Sampling}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {3}, pages = {447--457}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2474401}, doi = {10.1109/TCAD.2015.2474401}, timestamp = {Wed, 07 Dec 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/LanPC16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/LangeSJHCAS16, author = {Andr{\'{e}} Lange and Christoph Sohrmann and Roland Jancke and Joachim Haase and Binjie Cheng and Asen Asenov and Ulf Schlichtmann}, title = {Multivariate Modeling of Variability Supporting Non-Gaussian and Correlated Parameters}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {2}, pages = {197--210}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2459042}, doi = {10.1109/TCAD.2015.2459042}, timestamp = {Tue, 29 Dec 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/LangeSJHCAS16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/LeeF16, author = {Haeseung Lee and Mohammad Abdullah Al Faruque}, title = {Run-Time Scheduling Framework for Event-Driven Applications on a GPU-Based Embedded System}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {12}, pages = {1956--1967}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2547916}, doi = {10.1109/TCAD.2016.2547916}, timestamp = {Thu, 25 Mar 2021 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/LeeF16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/LeeHL16, author = {Hung{-}I Lee and Chen{-}Yo Han and James Chien{-}Mo Li}, title = {A Multicircuit Simulator Based on Inverse Jacobian Matrix Reuse}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {7}, pages = {1130--1137}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2501308}, doi = {10.1109/TCAD.2015.2501308}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/LeeHL16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/LeiM16, author = {Seong{-}I Lei and Wai{-}Kei Mak}, title = {Optimizing Pin Assignment and Escape Routing for Blind-via-Based PCBs}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {2}, pages = {246--259}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2460458}, doi = {10.1109/TCAD.2015.2460458}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/LeiM16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/LiXLXCJJ16, author = {Tianjian Li and Feng Xie and Xiaoyao Liang and Qiang Xu and Krishnendu Chakrabarty and Naifeng Jing and Li Jiang}, title = {A Novel Test Method for Metallic CNTs in CNFET-Based SRAMs}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {7}, pages = {1192--1205}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2512909}, doi = {10.1109/TCAD.2015.2512909}, timestamp = {Tue, 21 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/LiXLXCJJ16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/LiangSRC16, author = {Yun Liang and Muhammad Teguh Satria and Kyle Rupnow and Deming Chen}, title = {An Accurate {GPU} Performance Model for Effective Control Flow Divergence Optimization}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {7}, pages = {1165--1178}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2501303}, doi = {10.1109/TCAD.2015.2501303}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/LiangSRC16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/LiaoTYTSZZL16, author = {Changhai Liao and Jun Tao and Handi Yu and Zhangwen Tang and Yangfeng Su and Dian Zhou and Xuan Zeng and Xin Li}, title = {Efficient Hybrid Performance Modeling for Analog Circuits Using Hierarchical Shrinkage Priors}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {12}, pages = {2148--2152}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2543021}, doi = {10.1109/TCAD.2016.2543021}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/LiaoTYTSZZL16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/LiaoTZSZ016, author = {Changhai Liao and Jun Tao and Xuan Zeng and Yangfeng Su and Dian Zhou and Xin Li}, title = {Efficient Spatial Variation Modeling of Nanoscale Integrated Circuits Via Hidden Markov Tree}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {6}, pages = {971--984}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2481868}, doi = {10.1109/TCAD.2015.2481868}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/LiaoTZSZ016.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/LifaEP16, author = {Adrian Alin Lifa and Petru Eles and Zebo Peng}, title = {A Reconfigurable Framework for Performance Enhancement With Dynamic {FPGA} Configuration Prefetching}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {1}, pages = {100--113}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2448694}, doi = {10.1109/TCAD.2015.2448694}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/LifaEP16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/LinCLG16, author = {Mark Po{-}Hung Lin and Po{-}Hsun Chang and Shuenn{-}Yuh Lee and Helmut E. Graeb}, title = {DeMixGen: Deterministic Mixed-Signal Layout Generation With Separated Analog and Digital Signal Paths}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {8}, pages = {1229--1242}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2501295}, doi = {10.1109/TCAD.2015.2501295}, timestamp = {Sun, 12 Nov 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/LinCLG16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/LinWCP16, author = {Xue Lin and Yanzhi Wang and Naehyuck Chang and Massoud Pedram}, title = {Concurrent Task Scheduling and Dynamic Voltage and Frequency Scaling in a Real-Time Embedded System With Energy Harvesting}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {11}, pages = {1890--1902}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2523450}, doi = {10.1109/TCAD.2016.2523450}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/LinWCP16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/LiuFC16, author = {Iou{-}Jen Liu and Shao{-}Yun Fang and Yao{-}Wen Chang}, title = {Overlay-Aware Detailed Routing for Self-Aligned Double Patterning Lithography Using the Cut Process}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {9}, pages = {1519--1531}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2513670}, doi = {10.1109/TCAD.2015.2513670}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/LiuFC16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/LiuHLM16, author = {Junxiu Liu and Jim Harkin and Yuhua Li and Liam P. Maguire}, title = {Fault-Tolerant Networks-on-Chip Routing With Coarse and Fine-Grained Look-Ahead}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {2}, pages = {260--273}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2459050}, doi = {10.1109/TCAD.2015.2459050}, timestamp = {Wed, 01 Sep 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/LiuHLM16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/LiuP16, author = {Lechang Liu and Ramesh K. Pokharel}, title = {Compact Modeling of Phase-Locked Loop Frequency Synthesizer for Transient Phase Noise and Jitter Simulation}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {1}, pages = {166--170}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2472018}, doi = {10.1109/TCAD.2015.2472018}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/LiuP16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/LongLLZZSS16, author = {Linbo Long and Duo Liu and Liang Liang and Xiao Zhu and Kan Zhong and Zili Shao and Edwin Hsing{-}Mean Sha}, title = {Morphable Resistive Memory Optimization for Mobile Virtualization}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {6}, pages = {891--904}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2495264}, doi = {10.1109/TCAD.2015.2495264}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/LongLLZZSS16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/LukasiewyczKS16, author = {Martin Lukasiewycz and Matthias Kauer and Sebastian Steinhorst}, title = {Synthesis of Active Cell Balancing Architectures for Battery Packs}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {11}, pages = {1876--1889}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2531049}, doi = {10.1109/TCAD.2016.2531049}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/LukasiewyczKS16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/MagerlCB16, author = {Marko Magerl and Vladimir Ceperic and Adrijan Baric}, title = {Echo State Networks for Black-Box Modeling of Integrated Circuits}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {8}, pages = {1309--1317}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2501312}, doi = {10.1109/TCAD.2015.2501312}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/MagerlCB16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/MahmutogluD16, author = {Ahmet Gokcen Mahmutoglu and Alper Demir}, title = {Non-Monte Carlo Analysis of Low-Frequency Noise: Exposition of Intricate Nonstationary Behavior and Comparison With Legacy Models}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {11}, pages = {1825--1835}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2529431}, doi = {10.1109/TCAD.2016.2529431}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/MahmutogluD16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/MeiSWZCC16, author = {Qinggao Mei and Wim Schoenmaker and Shih{-}Hung Weng and Hao Zhuang and Chung{-}Kuan Cheng and Quan Chen}, title = {An Efficient Transient Electro-Thermal Simulation Framework for Power Integrated Circuits}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {5}, pages = {832--843}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2488494}, doi = {10.1109/TCAD.2015.2488494}, timestamp = {Tue, 13 Aug 2024 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/MeiSWZCC16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/MengSR16, author = {Kuo{-}Hsuan Meng and Vrashank Shukla and Elyse Rosenbaum}, title = {Full-Component Modeling and Simulation of Charged Device Model {ESD}}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {7}, pages = {1105--1113}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2495196}, doi = {10.1109/TCAD.2015.2495196}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/MengSR16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/MineoPAPC16, author = {Andrea Mineo and Maurizio Palesi and Giuseppe Ascia and Partha Pratim Pande and Vincenzo Catania}, title = {On-Chip Communication Energy Reduction Through Reliability Aware Adaptive Voltage Swing Scaling}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {11}, pages = {1769--1782}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2524556}, doi = {10.1109/TCAD.2016.2524556}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/MineoPAPC16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/MohammadiGM16, author = {Hassan Ghasemzadeh Mohammadi and Pierre{-}Emmanuel Gaillardon and Giovanni De Micheli}, title = {Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {12}, pages = {1995--2007}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2547908}, doi = {10.1109/TCAD.2016.2547908}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/MohammadiGM16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/MoudallalN16, author = {Zahi Moudallal and Farid N. Najm}, title = {Generating Current Budgets to Guarantee Power Grid Safety}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {11}, pages = {1914--1927}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2524659}, doi = {10.1109/TCAD.2016.2524659}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/MoudallalN16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/MukherjeeR16, author = {Shyamapada Mukherjee and Suchismita Roy}, title = {Nearly-2-SAT Solutions for Segmented-Channel Routing}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {1}, pages = {128--140}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2446950}, doi = {10.1109/TCAD.2015.2446950}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/MukherjeeR16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/NandiTKK16, author = {Prajit Nandi and Hirak Talukdar and Dhiraj Kumar and Ashvinkumar G. Katakwar}, title = {A Novel Approach to Design {SAR-ADC:} Design Partitioning Method}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {3}, pages = {346--356}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2474379}, doi = {10.1109/TCAD.2015.2474379}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/NandiTKK16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/NaneSPCFCCHBFAB16, author = {Razvan Nane and Vlad Mihai Sima and Christian Pilato and Jongsok Choi and Blair Fort and Andrew Canis and Yu Ting Chen and Hsuan Hsiao and Stephen Dean Brown and Fabrizio Ferrandi and Jason Helge Anderson and Koen Bertels}, title = {A Survey and Evaluation of {FPGA} High-Level Synthesis Tools}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {10}, pages = {1591--1604}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2513673}, doi = {10.1109/TCAD.2015.2513673}, timestamp = {Fri, 09 Apr 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/NaneSPCFCCHBFAB16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/NarayananAD16, author = {Vijaykrishnan Narayanan and Charles J. Alpert and Sara Dailey}, title = {Editorial}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {3}, pages = {345}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2528438}, doi = {10.1109/TCAD.2016.2528438}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/NarayananAD16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/NiDSGY16, author = {Leibin Ni and Sai Manoj P. D. and Yang Song and Chenjie Gu and Hao Yu}, title = {A Zonotoped Macromodeling for Eye-Diagram Verification of High-Speed {I/O} Links With Jitter and Parameter Variations}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {6}, pages = {1040--1051}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2481873}, doi = {10.1109/TCAD.2015.2481873}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/NiDSGY16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/NiemannWMTD16, author = {Philipp Niemann and Robert Wille and D. Michael Miller and Mitchell A. Thornton and Rolf Drechsler}, title = {QMDDs: Efficient Quantum Function Representation and Manipulation}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {1}, pages = {86--99}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2459034}, doi = {10.1109/TCAD.2015.2459034}, timestamp = {Tue, 24 Nov 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/NiemannWMTD16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/OuTLWC16, author = {Hung{-}Chih Ou and Kai{-}Han Tseng and Jhao{-}Yan Liu and I{-}Peng Wu and Yao{-}Wen Chang}, title = {Layout-Dependent Effects-Aware Analytical Analog Placement}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {8}, pages = {1243--1254}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2501293}, doi = {10.1109/TCAD.2015.2501293}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/OuTLWC16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/OxmanW16, author = {Gadi Oxman and Shlomo Weiss}, title = {An NoC Simulator That Supports Deflection Routing, {GPU/CPU} Integration, and Co-Simulation}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {10}, pages = {1667--1680}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2527698}, doi = {10.1109/TCAD.2016.2527698}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/OxmanW16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/OyaroT16, author = {Denis Oyaro and Piero Triverio}, title = {TurboMOR-RC: An Efficient Model Order Reduction Technique for {RC} Networks With Many Ports}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {10}, pages = {1695--1706}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2531046}, doi = {10.1109/TCAD.2016.2531046}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/OyaroT16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/PalI16, author = {Soumitra Pal and Aminul Islam}, title = {Variation Tolerant Differential 8T {SRAM} Cell for Ultralow Power Applications}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {4}, pages = {549--558}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2474408}, doi = {10.1109/TCAD.2015.2474408}, timestamp = {Wed, 27 Jan 2021 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/PalI16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/PalaniswamyTH16, author = {Ashok Kumar Palaniswamy and Spyros Tragoudas and Themistoklis Haniotakis}, title = {{ATPG} for Delay Defects in Current Mode Threshold Logic Circuits}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {11}, pages = {1903--1913}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2533863}, doi = {10.1109/TCAD.2016.2533863}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/PalaniswamyTH16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/PanLXS16, author = {Yubiao Pan and Yongkun Li and Yinlong Xu and Biaobiao Shen}, title = {{DCS:} Diagonal Coding Scheme for Enhancing the Endurance of SSD-Based {RAID} Arrays}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {8}, pages = {1372--1385}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2504333}, doi = {10.1109/TCAD.2015.2504333}, timestamp = {Mon, 16 Jan 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/PanLXS16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ParkTS16, author = {Jea Woo Park and Robert Todd and Xiaoyu Song}, title = {Geometric Pattern Match Using Edge Driven Dissected Rectangles and Vector Space}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {12}, pages = {2046--2055}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2535908}, doi = {10.1109/TCAD.2016.2535908}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ParkTS16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/Pomeranz16, author = {Irith Pomeranz}, title = {Balancing the Numbers of Detected Faults for Improved Test Set Quality}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {2}, pages = {337--341}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2460463}, doi = {10.1109/TCAD.2015.2460463}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/Pomeranz16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/Pomeranz16a, author = {Irith Pomeranz}, title = {Static Test Compaction for Functional Test Sequences With Restoration of Functional Switching Activity}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {10}, pages = {1755--1762}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2512931}, doi = {10.1109/TCAD.2015.2512931}, timestamp = {Tue, 16 Aug 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/Pomeranz16a.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/PosserMJRS16, author = {Gracieli Posser and Vivek Mishra and Palkesh Jain and Ricardo Reis and Sachin S. Sapatnekar}, title = {Cell-Internal Electromigration: Analysis and Pin Placement Based Optimization}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {2}, pages = {220--231}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2456427}, doi = {10.1109/TCAD.2015.2456427}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/PosserMJRS16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/PrussKE16, author = {Tim Pruss and Priyank Kalla and Florian Enescu}, title = {Efficient Symbolic Computation for Word-Level Abstraction From Combinational Circuits for Verification Over Finite Fields}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {7}, pages = {1206--1218}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2501301}, doi = {10.1109/TCAD.2015.2501301}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/PrussKE16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/PsarrasLSND16, author = {Anastasios Psarras and Junghee Lee and Ioannis Seitanidis and Chrysostomos Nicopoulos and Giorgos Dimitrakopoulos}, title = {PhaseNoC: Versatile Network Traffic Isolation Through TDM-Scheduled Virtual Channels}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {5}, pages = {844--857}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2488490}, doi = {10.1109/TCAD.2015.2488490}, timestamp = {Mon, 05 Feb 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/PsarrasLSND16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/QianJBTMM16, author = {Zhiliang Qian and Da{-}Cheng Juan and Paul Bogdan and Chi{-}Ying Tsui and Diana Marculescu and Radu Marculescu}, title = {A Support Vector Regression (SVR)-Based Latency Model for Network-on-Chip (NoC) Architectures}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {3}, pages = {471--484}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2474393}, doi = {10.1109/TCAD.2015.2474393}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/QianJBTMM16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/RanaBBNAS16, author = {Vincenzo Rana and Ivan Beretta and Francesco Bruschi and Alessandro Antonio Nacci and David Atienza and Donatella Sciuto}, title = {Efficient Hardware Design of Iterative Stencil Loops}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {12}, pages = {2018--2031}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2545408}, doi = {10.1109/TCAD.2016.2545408}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/RanaBBNAS16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ReeceR16, author = {Trey Reece and William H. Robinson}, title = {Detection of Hardware Trojans in Third-Party Intellectual Property Using Untrusted Modules}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {3}, pages = {357--366}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2459038}, doi = {10.1109/TCAD.2015.2459038}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ReeceR16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/RonakF16, author = {Bajaj Ronak and Suhaib A. Fahmy}, title = {Mapping for Maximum Performance on {FPGA} {DSP} Blocks}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {4}, pages = {573--585}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2474363}, doi = {10.1109/TCAD.2015.2474363}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/RonakF16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/RoyCPP16, author = {Subhendu Roy and Mihir R. Choudhury and Ruchir Puri and David Z. Pan}, title = {Polynomial Time Algorithm for Area and Power Efficient Adder Synthesis in High-Performance Designs}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {5}, pages = {820--831}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2481794}, doi = {10.1109/TCAD.2015.2481794}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/RoyCPP16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/RoyLSUP16, author = {Subhendu Roy and Derong Liu and Jagmohan Singh and Junhyung Um and David Z. Pan}, title = {{OSFA:} {A} New Paradigm of Aging Aware Gate-Sizing for Power/Performance Optimizations Under Multiple Operating Conditions}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {10}, pages = {1618--1629}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2523439}, doi = {10.1109/TCAD.2016.2523439}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/RoyLSUP16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/SagstetterWSLC16, author = {Florian Sagstetter and Peter Waszecki and Sebastian Steinhorst and Martin Lukasiewycz and Samarjit Chakraborty}, title = {Multischedule Synthesis for Variant Management in Automotive Time-Triggered Systems}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {4}, pages = {637--650}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2488480}, doi = {10.1109/TCAD.2015.2488480}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/SagstetterWSLC16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/SamalPSSDL16, author = {Sandeep Kumar Samal and Shreepad Panth and Kambiz Samadi and Mehdi Saedi and Yang Du and Sung Kyu Lim}, title = {Adaptive Regression-Based Thermal Modeling and Optimization for Monolithic 3-D ICs}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {10}, pages = {1707--1720}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2523983}, doi = {10.1109/TCAD.2016.2523983}, timestamp = {Sun, 02 Oct 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/SamalPSSDL16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/SavojMB16, author = {Hamid Savoj and Alan Mishchenko and Robert K. Brayton}, title = {m-Inductive Property of Sequential Circuits}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {6}, pages = {919--930}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2481860}, doi = {10.1109/TCAD.2015.2481860}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/SavojMB16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/Schafer16, author = {Benjamin Carri{\'{o}}n Sch{\"{a}}fer}, title = {Probabilistic Multiknob High-Level Synthesis Design Space Exploration Acceleration}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {3}, pages = {394--406}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2472007}, doi = {10.1109/TCAD.2015.2472007}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/Schafer16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/SeoLK16, author = {Sungyoul Seo and Yong Lee and Sungho Kang}, title = {Tri-State Coding Using Reconfiguration of Twisted Ring Counter for Test Data Compression}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {2}, pages = {274--284}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2413416}, doi = {10.1109/TCAD.2015.2413416}, timestamp = {Wed, 28 Feb 2024 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/SeoLK16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ShafikY0MMA16, author = {Rishad A. Shafik and Sheng Yang and Anup Das and Luis Alfonso Maeda{-}Nunez and Geoff V. Merrett and Bashir M. Al{-}Hashimi}, title = {Learning Transfer-Based Adaptive Energy Minimization in Embedded Systems}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {6}, pages = {877--890}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2481867}, doi = {10.1109/TCAD.2015.2481867}, timestamp = {Mon, 15 May 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ShafikY0MMA16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/SharifiB16, author = {Mohammad Javad Sharifi and Davoud Bahrepour}, title = {A Multiloop and Full Amplitude Hysteresis Model for Molecular Electronics}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {2}, pages = {187--196}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2409254}, doi = {10.1109/TCAD.2015.2409254}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/SharifiB16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ShiN16, author = {Xiaobing Shi and Nicola Nicolici}, title = {On-Chip Cube-Based Constrained-Random Stimuli Generation for Post-Silicon Validation}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {6}, pages = {1012--1025}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2481874}, doi = {10.1109/TCAD.2015.2481874}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ShiN16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ShiWZXLS16, author = {Liang Shi and Kaijie Wu and Mengying Zhao and Chun Jason Xue and Duo Liu and Edwin Hsing{-}Mean Sha}, title = {Retention Trimming for Lifetime Improvement of Flash Memory Storage Systems}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {1}, pages = {58--71}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2453369}, doi = {10.1109/TCAD.2015.2453369}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ShiWZXLS16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ShyuLLHC16, author = {Ya{-}Ting Shyu and Jai{-}Ming Lin and Che{-}Chun Lin and Chun{-}Po Huang and Soon{-}Jyh Chang}, title = {An Efficient and Effective Methodology to Control Turn-On Sequence of Power Switches for Power Gating Designs}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {10}, pages = {1730--1743}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2523916}, doi = {10.1109/TCAD.2016.2523916}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ShyuLLHC16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/SimLSL16, author = {Hyeon Uk Sim and Hongsik Lee and Seongseok Seo and Jongeun Lee}, title = {Mapping Imperfect Loops to Coarse-Grained Reconfigurable Architectures}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {7}, pages = {1092--1104}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2504918}, doi = {10.1109/TCAD.2015.2504918}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/SimLSL16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/SinghSKH16, author = {Amit Kumar Singh and Muhammad Shafique and Akash Kumar and J{\"{o}}rg Henkel}, title = {Resource and Throughput Aware Execution Trace Analysis for Efficient Run-Time Mapping on MPSoCs}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {1}, pages = {72--85}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2446938}, doi = {10.1109/TCAD.2015.2446938}, timestamp = {Tue, 07 May 2024 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/SinghSKH16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/SioziosS16, author = {Kostas Siozios and Dimitrios Soudris}, title = {A Customizable Framework for Application Implementation onto 3-D FPGAs}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {11}, pages = {1783--1796}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2529421}, doi = {10.1109/TCAD.2016.2529421}, timestamp = {Tue, 07 May 2024 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/SioziosS16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/SiyoumGC16, author = {Firew Siyoum and Marc Geilen and Henk Corporaal}, title = {End-to-End Latency Analysis of Dataflow Scenarios Mapped Onto Shared Heterogeneous Resources}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {4}, pages = {535--548}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2472004}, doi = {10.1109/TCAD.2015.2472004}, timestamp = {Mon, 26 Oct 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/SiyoumGC16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/SongPCL16, author = {Taigon Song and Shreepad Panth and Yoo{-}Jin Chae and Sung Kyu Lim}, title = {More Power Reduction With 3-Tier Logic-on-Logic 3-D ICs}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {12}, pages = {2056--2067}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2550583}, doi = {10.1109/TCAD.2016.2550583}, timestamp = {Sun, 02 Oct 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/SongPCL16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/SuHTCB16, author = {Yu{-}Hsuan Su and Yu{-}Chen Huang and Liang{-}Chun Tsai and Yao{-}Wen Chang and Shayak Banerjee}, title = {Fast Lithographic Mask Optimization Considering Process Variation}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {8}, pages = {1345--1357}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2514082}, doi = {10.1109/TCAD.2015.2514082}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/SuHTCB16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/SureshK16, author = {Vikram B. Suresh and Sandip Kundu}, title = {Managing Test Coverage Uncertainty due to Random Noise in Nano-CMOS: {A} Case-Study on an {SRAM} Array}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {1}, pages = {155--165}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2449236}, doi = {10.1109/TCAD.2015.2449236}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/SureshK16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/TaatizadehN16, author = {Pouya Taatizadeh and Nicola Nicolici}, title = {Automated Selection of Assertions for Bit-Flip Detection During Post-Silicon Validation}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {12}, pages = {2118--2130}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2538087}, doi = {10.1109/TCAD.2016.2538087}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/TaatizadehN16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/TaoLZ016, author = {Jun Tao and Changhai Liao and Xuan Zeng and Xin Li}, title = {Harvesting Design Knowledge From the Internet: High-Dimensional Performance Tradeoff Modeling for Large-Scale Analog Circuits}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {1}, pages = {23--36}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2449240}, doi = {10.1109/TCAD.2015.2449240}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/TaoLZ016.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/TsengLLHS16, author = {Tsun{-}Ming Tseng and Bing Li and Mengchu Li and Tsung{-}Yi Ho and Ulf Schlichtmann}, title = {Reliability-Aware Synthesis With Dynamic Device Mapping and Fluid Routing for Flow-Based Microfluidic Biochips}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {12}, pages = {1981--1994}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2547902}, doi = {10.1109/TCAD.2016.2547902}, timestamp = {Tue, 29 Dec 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/TsengLLHS16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/VintanCIC16, author = {Lucian Vintan and Radu Chis and Muhammad Ali Ismail and Cristian Cotofana}, title = {Improving Computing Systems Automatic Multiobjective Optimization Through Meta-Optimization}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {7}, pages = {1125--1129}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2501299}, doi = {10.1109/TCAD.2015.2501299}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/VintanCIC16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/WangCZS0KG16, author = {Fa Wang and Paolo Cachecho and Wangyang Zhang and Shupeng Sun and Xin Li and Rouwaida Kanj and Chenjie Gu}, title = {Bayesian Model Fusion: Large-Scale Performance Modeling of Analog and Mixed-Signal Circuits by Reusing Early-Stage Data}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {8}, pages = {1255--1268}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2504329}, doi = {10.1109/TCAD.2015.2504329}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/WangCZS0KG16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/WangG16, author = {Wei{-}Che Wang and Puneet Gupta}, title = {Efficient Layout Generation and Design Evaluation of Vertical Channel Devices}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {9}, pages = {1449--1460}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2513674}, doi = {10.1109/TCAD.2015.2513674}, timestamp = {Thu, 28 Oct 2021 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/WangG16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/WangK16, author = {Xueyang Wang and Ramesh Karri}, title = {Reusing Hardware Performance Counters to Detect and Identify Kernel Control-Flow Modifying Rootkits}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {3}, pages = {485--498}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2474374}, doi = {10.1109/TCAD.2015.2474374}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/WangK16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/WangLL16, author = {Ya Wang and Peng Li and Suming Lai}, title = {Robust and Efficient Transistor-Level Envelope-Following Analysis of {PWM/PFM/PSM} {DC-DC} Converters}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {11}, pages = {1836--1847}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2524565}, doi = {10.1109/TCAD.2016.2524565}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/WangLL16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/WangLLW0K16, author = {Jian Wang and Huawei Li and Tao Lv and Tiancheng Wang and Xiaowei Li and Sandip Kundu}, title = {Abstraction-Guided Simulation Using Markov Analysis for Functional Verification}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {2}, pages = {285--297}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2419622}, doi = {10.1109/TCAD.2015.2419622}, timestamp = {Thu, 11 May 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/WangLLW0K16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/WangLWLSLCY16, author = {Yiqun Wang and Yongpan Liu and Cong Wang and Zewei Li and Xiao Sheng and Hyung Gyu Lee and Naehyuck Chang and Huazhong Yang}, title = {Storage-Less and Converter-Less Photovoltaic Energy Harvesting With Maximum Power Point Tracking for Internet of Things}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {2}, pages = {173--186}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2446937}, doi = {10.1109/TCAD.2015.2446937}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/WangLWLSLCY16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/WangZXLCS16, author = {Tao Wang and Chun Zhang and Jinjun Xiong and Pei{-}Wen Luo and Liang{-}Chia Cheng and Yiyu Shi}, title = {On the Optimal Threshold Voltage Computation of On-Chip Noise Sensors}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {10}, pages = {1744--1754}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2513007}, doi = {10.1109/TCAD.2015.2513007}, timestamp = {Tue, 21 Mar 2023 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/WangZXLCS16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/WeberRD16, author = {Stephan Weber and Tiago Ressurreicao and C{\^{a}}ndido Duarte}, title = {Yield Prediction With a New Generalized Process Capability Index Applicable to Non-Normal Data}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {6}, pages = {931--942}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2481865}, doi = {10.1109/TCAD.2015.2481865}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/WeberRD16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/WeiDZQP16, author = {Debao Wei and Libao Deng and Peng Zhang and Liyan Qiao and Xiyuan Peng}, title = {{NRC:} {A} Nibble Remapping Coding Strategy for {NAND} Flash Reliability Extension}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {11}, pages = {1942--1946}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2533861}, doi = {10.1109/TCAD.2016.2533861}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/WeiDZQP16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/WuC16, author = {Gang Wu and Chris Chu}, title = {Detailed Placement Algorithm for {VLSI} Design With Double-Row Height Standard Cells}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {9}, pages = {1569--1573}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2511141}, doi = {10.1109/TCAD.2015.2511141}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/WuC16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/WuGHWWM16, author = {Tony F. Wu and Karthik Ganesan and Yunqing Alexander Hu and H.{-}S. Philip Wong and S. Simon Wong and Subhasish Mitra}, title = {{TPAD:} Hardware Trojan Prevention and Detection for Trusted Integrated Circuits}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {4}, pages = {521--534}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2474373}, doi = {10.1109/TCAD.2015.2474373}, timestamp = {Thu, 10 Nov 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/WuGHWWM16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/XiangSBWL16, author = {Dong Xiang and Kele Shen and Bhargab B. Bhattacharya and Xiaoqing Wen and Xijiang Lin}, title = {Thermal-Aware Small-Delay Defect Testing in Integrated Circuits for Mitigating Overkill}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {3}, pages = {499--512}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2474365}, doi = {10.1109/TCAD.2015.2474365}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/XiangSBWL16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/XieSCP16, author = {Qing Xie and Donghwa Shin and Naehyuck Chang and Massoud Pedram}, title = {Joint Charge and Thermal Management for Batteries in Portable Systems With Hybrid Power Sources}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {4}, pages = {611--622}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2474410}, doi = {10.1109/TCAD.2015.2474410}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/XieSCP16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/Yan16, author = {Jin{-}Tai Yan}, title = {Efficient Layer Assignment of Bus-Oriented Nets in High-Speed {PCB} Designs}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {8}, pages = {1332--1344}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2504898}, doi = {10.1109/TCAD.2015.2504898}, timestamp = {Sat, 09 Apr 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/Yan16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/YangCKT16, author = {Ming{-}Chang Yang and Yuan{-}Hao Chang and Yuan{-}Hung Kuan and Che{-}Wei Tsao}, title = {Graceful Space Degradation: An Uneven Space Management for Flash Storage Devices}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {9}, pages = {1425--1434}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2512902}, doi = {10.1109/TCAD.2015.2512902}, timestamp = {Mon, 26 Jun 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/YangCKT16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/YangCT16, author = {Joon{-}Sung Yang and Jinsuk Chung and Nur A. Touba}, title = {Enhancing Superset X-Canceling Method With Relaxed Constraints on Fault Observation}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {2}, pages = {298--308}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2459035}, doi = {10.1109/TCAD.2015.2459035}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/YangCT16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/YangLPZYZZ16, author = {Yunfeng Yang and Wai{-}Shing Luk and David Z. Pan and Hai Zhou and Changhao Yan and Dian Zhou and Xuan Zeng}, title = {Layout Decomposition Co-Optimization for Hybrid E-Beam and Multiple Patterning Lithography}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {9}, pages = {1532--1545}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2512903}, doi = {10.1109/TCAD.2015.2512903}, timestamp = {Wed, 16 Aug 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/YangLPZYZZ16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/YangWZCZCL16, author = {Jianlei Yang and Peiyuan Wang and Yaojun Zhang and Yuanqing Cheng and Weisheng Zhao and Yiran Chen and Hai (Helen) Li}, title = {Radiation-Induced Soft Error Analysis of {STT-MRAM:} {A} Device to Circuit Approach}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {3}, pages = {380--393}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2474366}, doi = {10.1109/TCAD.2015.2474366}, timestamp = {Mon, 04 Jul 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/YangWZCZCL16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/YaoWSHC16, author = {Hailong Yao and Qin Wang and Yiren Shen and Tsung{-}Yi Ho and Yici Cai}, title = {Integrated Functional and Washing Routing Optimization for Cross-Contamination Removal in Digital Microfluidic Biochips}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {8}, pages = {1283--1296}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2504397}, doi = {10.1109/TCAD.2015.2504397}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/YaoWSHC16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/YasinRSK16, author = {Muhammad Yasin and Jeyavijayan (JV) Rajendran and Ozgur Sinanoglu and Ramesh Karri}, title = {On Improving the Security of Logic Locking}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {9}, pages = {1411--1424}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2511144}, doi = {10.1109/TCAD.2015.2511144}, timestamp = {Mon, 28 Aug 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/YasinRSK16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/YeFYCT16, author = {Fangming Ye and Farshad Firouzi and Yang Yang and Krishnendu Chakrabarty and Mehdi Baradaran Tahoori}, title = {On-Chip Droop-Induced Circuit Delay Prediction Based on Support-Vector Machines}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {4}, pages = {665--678}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2474392}, doi = {10.1109/TCAD.2015.2474392}, timestamp = {Mon, 03 Jan 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/YeFYCT16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/YeZCG16, author = {Fangming Ye and Zhaobo Zhang and Krishnendu Chakrabarty and Xinli Gu}, title = {Adaptive Board-Level Functional Fault Diagnosis Using Incremental Decision Trees}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {2}, pages = {323--336}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2459046}, doi = {10.1109/TCAD.2015.2459046}, timestamp = {Mon, 03 Jan 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/YeZCG16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/YinGLLW16, author = {Shouyi Yin and Jiangyuan Gu and Dajiang Liu and Leibo Liu and Shaojun Wei}, title = {Joint Modulo Scheduling and V\({}_{\mbox{dd}}\) Assignment for Loop Mapping on Dual- V\({}_{\mbox{dd}}\) CGRAs}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {9}, pages = {1475--1488}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2512900}, doi = {10.1109/TCAD.2015.2512900}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/YinGLLW16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/YuBLRC16, author = {Cunxi Yu and Walter Brown and Duo Liu and Andr{\'{e}} Rossi and Maciej J. Ciesielski}, title = {Formal Verification of Arithmetic Circuits by Function Extraction}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {12}, pages = {2131--2142}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2547898}, doi = {10.1109/TCAD.2016.2547898}, timestamp = {Sun, 02 Oct 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/YuBLRC16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/YuSHEAB16, author = {Li Yu and Sharad Saxena and Christopher Hess and Ibrahim Abe M. Elfadel and Dimitri A. Antoniadis and Duane S. Boning}, title = {Compact Model Parameter Extraction Using Bayesian Inference, Incomplete New Measurements, and Optimal Bias Selection}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {7}, pages = {1138--1150}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2514083}, doi = {10.1109/TCAD.2015.2514083}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/YuSHEAB16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ZhangLLXLWY16, author = {Daming Zhang and Yongpan Liu and Jinyang Li and Chun Jason Xue and Xueqing Li and Yu Wang and Huazhong Yang}, title = {Solar Power Prediction Assisted Intra-task Scheduling for Nonvolatile Sensor Nodes}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {5}, pages = {724--737}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2527710}, doi = {10.1109/TCAD.2016.2527710}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ZhangLLXLWY16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ZhengDRZP16, author = {Bowen Zheng and Peng Deng and Anguluri Rajasekhar and Qi Zhu and Fabio Pasqualetti}, title = {Cross-Layer Codesign for Secure Cyber-Physical Systems}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {5}, pages = {699--711}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2523937}, doi = {10.1109/TCAD.2016.2523937}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ZhengDRZP16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ZhengYB16, author = {Yu Zheng and Shuo Yang and Swarup Bhunia}, title = {SeMIA: Self-Similarity-Based {IC} Integrity Analysis}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {1}, pages = {37--48}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2449231}, doi = {10.1109/TCAD.2015.2449231}, timestamp = {Tue, 07 May 2024 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ZhengYB16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ZhongLLZLWS16, author = {Kan Zhong and Duo Liu and Liang Liang and Xiao Zhu and Linbo Long and Yi Wang and Edwin Hsing{-}Mean Sha}, title = {Energy-Efficient In-Memory Paging for Smartphones}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {10}, pages = {1577--1590}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2512904}, doi = {10.1109/TCAD.2015.2512904}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ZhongLLZLWS16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ZhouWCYHM16, author = {Junlong Zhou and Tongquan Wei and Mingsong Chen and Jianming Yan and Xiaobo Sharon Hu and Yue Ma}, title = {Thermal-Aware Task Scheduling for Energy Minimization in Heterogeneous Real-Time MPSoC Systems}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {8}, pages = {1269--1282}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2501286}, doi = {10.1109/TCAD.2015.2501286}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ZhouWCYHM16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ZhouWLL016, author = {Yanhong Zhou and Tiancheng Wang and Huawei Li and Tao Lv and Xiaowei Li}, title = {Functional Test Generation for Hard-to-Reach States Using Path Constraint Solving}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {6}, pages = {999--1011}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2481863}, doi = {10.1109/TCAD.2015.2481863}, timestamp = {Thu, 11 May 2023 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ZhouWLL016.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ZhouZSJCL16, author = {Bin Zhou and Wei Zhang and Thambipillai Srikanthan and Jason Teo Kian Jin and Vivek Chaturvedi and Tao Luo}, title = {Cost-efficient Acceleration of Hardware Trojan Detection Through Fan-Out Cone Analysis and Weighted Random Pattern Technique}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {5}, pages = {792--805}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2460551}, doi = {10.1109/TCAD.2015.2460551}, timestamp = {Mon, 14 Nov 2022 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/ZhouZSJCL16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ZhouZSQS16, author = {Yuhan Zhou and Yong Zhang and Vivek Sarin and Wangqi Qiu and Weiping Shi}, title = {Macro Model of Advanced Devices for Parasitic Extraction}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {10}, pages = {1721--1729}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2524577}, doi = {10.1109/TCAD.2016.2524577}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ZhouZSQS16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ZhuGBS16, author = {Xue{-}Yang Zhu and Marc Geilen and Twan Basten and Sander Stuijk}, title = {Multiconstraint Static Scheduling of Synchronous Dataflow Graphs Via Retiming and Unfolding}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {6}, pages = {905--918}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2495167}, doi = {10.1109/TCAD.2015.2495167}, timestamp = {Mon, 26 Oct 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/tcad/ZhuGBS16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ZhuYCP16, author = {Di Zhu and Siyu Yue and Naehyuck Chang and Massoud Pedram}, title = {Toward a Profitable Grid-Connected Hybrid Electrical Energy Storage System for Residential Use}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {7}, pages = {1151--1164}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2015.2501296}, doi = {10.1109/TCAD.2015.2501296}, timestamp = {Thu, 24 Sep 2020 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ZhuYCP16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/tcad/ZhuangYWKLZCC16, author = {Hao Zhuang and Wenjian Yu and Shih{-}Hung Weng and Ilgweon Kang and Jeng{-}Hau Lin and Xiang Zhang and Ryan Coutts and Chung{-}Kuan Cheng}, title = {Simulation Algorithms With Exponential Integration for Time-Domain Analysis of Large-Scale Power Delivery Networks}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {35}, number = {10}, pages = {1681--1694}, year = {2016}, url = {https://doi.org/10.1109/TCAD.2016.2523908}, doi = {10.1109/TCAD.2016.2523908}, timestamp = {Thu, 11 Aug 2022 01:00:00 +0200}, biburl = {https://dblp.org/rec/journals/tcad/ZhuangYWKLZCC16.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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