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@article{DBLP:journals/tcad/AdegbijaRPG18,
author = {Tosiron Adegbija and
Anita Rogacs and
Chandrakant Patel and
Ann Gordon{-}Ross},
title = {Microprocessor Optimizations for the Internet of Things: {A} Survey},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {1},
pages = {7--20},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2717782},
doi = {10.1109/TCAD.2017.2717782},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AdegbijaRPG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AghaieKA18,
author = {Anita Aghaie and
Mehran Mozaffari Kermani and
Reza Azarderakhsh},
title = {Reliable and Fault Diagnosis Architectures for Hardware and Software-Efficient
Block Cipher {KLEIN} Benchmarked on {FPGA}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {4},
pages = {901--905},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2740286},
doi = {10.1109/TCAD.2017.2740286},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AghaieKA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AhmedZTB18,
author = {Ibrahim Ahmed and
Shuze Zhao and
Olivier Trescases and
Vaughn Betz},
title = {Automatic Application-Specific Calibration to Enable Dynamic Voltage
Scaling in FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {12},
pages = {3095--3108},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2801222},
doi = {10.1109/TCAD.2018.2801222},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AhmedZTB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AlaghiQH18,
author = {Armin Alaghi and
Weikang Qian and
John P. Hayes},
title = {The Promise and Challenge of Stochastic Computing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {8},
pages = {1515--1531},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2778107},
doi = {10.1109/TCAD.2017.2778107},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AlaghiQH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AlanH18,
author = {Tanfer Alan and
J{\"{o}}rg Henkel},
title = {SlackHammer: Logic Synthesis for Graceful Errors Under Frequency Scaling},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2802--2811},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2858364},
doi = {10.1109/TCAD.2018.2858364},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AlanH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AlawiehWL18,
author = {Mohamed Baker Alawieh and
Fa Wang and
Xin Li},
title = {Identifying Wafer-Level Systematic Failure Patterns via Unsupervised
Learning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {4},
pages = {832--844},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2729469},
doi = {10.1109/TCAD.2017.2729469},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AlawiehWL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AlawiehWL18a,
author = {Mohamed Baker Alawieh and
Fa Wang and
Xin Li},
title = {Efficient Hierarchical Performance Modeling for Analog and Mixed-Signal
Circuits via Bayesian Co-Learning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {12},
pages = {2986--2998},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2789778},
doi = {10.1109/TCAD.2018.2789778},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AlawiehWL18a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AmirG18,
author = {Maral Amir and
Tony Givargis},
title = {Priority Neuron: {A} Resource-Aware Neural Network for Cyber-Physical
Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2732--2742},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857319},
doi = {10.1109/TCAD.2018.2857319},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AmirG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AndriCRB18,
author = {Renzo Andri and
Lukas Cavigelli and
Davide Rossi and
Luca Benini},
title = {YodaNN: An Architecture for Ultralow Power Binary-Weight {CNN} Acceleration},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {1},
pages = {48--60},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2682138},
doi = {10.1109/TCAD.2017.2682138},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AndriCRB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AngiziHBF18,
author = {Shaahin Angizi and
Zhezhi He and
Nader Bagherzadeh and
Deliang Fan},
title = {Design and Evaluation of a Spintronic In-Memory Processing Platform
for Nonvolatile Data Encryption},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {9},
pages = {1788--1801},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2774291},
doi = {10.1109/TCAD.2017.2774291},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AngiziHBF18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AnsariFBMKAP18,
author = {Mohammad Ansari and
Arash Fayyazi and
Ali BanaGozar and
Mohammad Ali Maleki and
Mehdi Kamal and
Ali Afzali{-}Kusha and
Massoud Pedram},
title = {{PHAX:} Physical Characteristics Aware Ex-Situ Training Framework
for Inverter-Based Memristive Neuromorphic Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {8},
pages = {1602--1613},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2764070},
doi = {10.1109/TCAD.2017.2764070},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AnsariFBMKAP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AnsariJKP18,
author = {Muhammad Adil Ansari and
Jihun Jung and
Dooyoung Kim and
Sungju Park},
title = {Time-Multiplexed 1687-Network for Test Cost Reduction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {8},
pages = {1681--1691},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2766146},
doi = {10.1109/TCAD.2017.2766146},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AnsariJKP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AnsariJKP18a,
author = {Muhammad Adil Ansari and
Jihun Jung and
Dooyoung Kim and
Sungju Park},
title = {Erratum to "Time-Multiplexed-Network for Test Cost Reduction"},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {9},
pages = {1912},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2861341},
doi = {10.1109/TCAD.2018.2861341},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AnsariJKP18a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AsokanNRST18,
author = {N. Asokan and
Thomas Nyman and
Norrathep Rattanavipanon and
Ahmad{-}Reza Sadeghi and
Gene Tsudik},
title = {{ASSURED:} Architecture for Secure Software Update of Realistic Embedded
Devices},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2290--2300},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2858422},
doi = {10.1109/TCAD.2018.2858422},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AsokanNRST18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AyupovYOKBO18,
author = {Andrey Ayupov and
Serif Yesil and
Muhammet Mustafa Ozdal and
Taemin Kim and
Steven M. Burns and
Ozcan Ozturk},
title = {A Template-Based Design Methodology for Graph-Parallel Hardware Accelerators},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {2},
pages = {420--430},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2706562},
doi = {10.1109/TCAD.2017.2706562},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AyupovYOKBO18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BaeHME18,
author = {Inpyo Bae and
Barend Harris and
Hyemi Min and
Bernhard Egger},
title = {Auto-Tuning CNNs for Coarse-Grained Reconfigurable Array-Based Accelerators},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2301--2310},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857278},
doi = {10.1109/TCAD.2018.2857278},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BaeHME18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BaileyKM18,
author = {Jonathan Bailey and
John Kloosterman and
Scott A. Mahlke},
title = {Scratch That (But Cache This): {A} Hybrid Register Cache/Scratchpad
for GPUs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2779--2789},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857043},
doi = {10.1109/TCAD.2018.2857043},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BaileyKM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BeaumontMSY18,
author = {Jonathan Beaumont and
Andrey Mokhov and
Danil Sokolov and
Alex Yakovlev},
title = {High-Level Asynchronous Concepts at the Interface Between Analog and
Digital Worlds},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {1},
pages = {61--74},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2748002},
doi = {10.1109/TCAD.2017.2748002},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BeaumontMSY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Bera18,
author = {Debajyoti Bera},
title = {Detection and Diagnosis of Single Faults in Quantum Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {3},
pages = {587--600},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2717783},
doi = {10.1109/TCAD.2017.2717783},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Bera18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BerryhillV18,
author = {Ryan Berryhill and
Andreas G. Veneris},
title = {Methodologies for Diagnosis of Unreachable States via Property Directed
Reachability},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {6},
pages = {1298--1311},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2747999},
doi = {10.1109/TCAD.2017.2747999},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BerryhillV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BoratenK18,
author = {Travis Boraten and
Avinash Karanth Kodi},
title = {Runtime Techniques to Mitigate Soft Errors in Network-on-Chip (NoC)
Architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {3},
pages = {682--695},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2664066},
doi = {10.1109/TCAD.2017.2664066},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BoratenK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BoseC18,
author = {Ananya Bose and
Abhijit Chandra},
title = {Conditional Differential Coefficients Method for the Realization of
Powers-of-Two {FIR} Filter},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {12},
pages = {3221--3225},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2801238},
doi = {10.1109/TCAD.2018.2801238},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BoseC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BurchardERSB18,
author = {Jan Burchard and
Dominik Erb and
Sudhakar M. Reddy and
Adit D. Singh and
Bernd Becker},
title = {On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware
Tests for Transistor Stuck-Off Faults in {CMOS} Logic Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {10},
pages = {2152--2165},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2772825},
doi = {10.1109/TCAD.2017.2772825},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/BurchardERSB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CardonaHAC18,
author = {Jordi Cardona and
Carles Hern{\'{a}}ndez and
Jaume Abella and
Francisco J. Cazorla},
title = {EOmesh: Combined Flow Balancing and Deterministic Routing for Reduced
{WCET} Estimates in Embedded Real-Time Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2451--2461},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857298},
doi = {10.1109/TCAD.2018.2857298},
timestamp = {Fri, 14 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CardonaHAC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChatterjeeSN18,
author = {Sandeep Chatterjee and
Valeriy Sukharev and
Farid N. Najm},
title = {Power Grid Electromigration Checking Using Physics-Based Models},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {7},
pages = {1317--1330},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2666723},
doi = {10.1109/TCAD.2017.2666723},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChatterjeeSN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChattopadhyayR18,
author = {Sudipta Chattopadhyay and
Abhik Roychoudhury},
title = {Symbolic Verification of Cache Side-Channel Freedom},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2812--2823},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2858402},
doi = {10.1109/TCAD.2018.2858402},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChattopadhyayR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenCWZR18,
author = {Jiajia Chen and
Chip{-}Hong Chang and
Yujia Wang and
Juan Zhao and
Susanto Rahardja},
title = {New Hardware and Power Efficient Sporadic Logarithmic Shifters for
{DSP} Applications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {4},
pages = {896--900},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2740300},
doi = {10.1109/TCAD.2017.2740300},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenCWZR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenGHY18,
author = {Gang Chen and
Nan Guan and
Biao Hu and
Wang Yi},
title = {{EDF-VD} Scheduling of Flexible Mixed-Criticality System With Multiple-Shot
Transitions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2393--2403},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857359},
doi = {10.1109/TCAD.2018.2857359},
timestamp = {Wed, 10 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ChenGHY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenLYWXWLY18,
author = {Xiaoming Chen and
Qiaoyi Liu and
Song Yao and
Jia Wang and
Qiang Xu and
Yu Wang and
Yongpan Liu and
Huazhong Yang},
title = {Hardware Trojan Detection in Third-Party Digital Intellectual Property
Cores by Multilevel Feature Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {7},
pages = {1370--1383},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2748021},
doi = {10.1109/TCAD.2017.2748021},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ChenLYWXWLY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenMMRTZ18,
author = {Michael Chen and
Elham K. Moghaddam and
Nilanjan Mukherjee and
Janusz Rajski and
Jerzy Tyszer and
Justyna Zawada},
title = {Hardware Protection via Logic Locking Test Points},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {12},
pages = {3020--3030},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2801240},
doi = {10.1109/TCAD.2018.2801240},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenMMRTZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenPCLKYY18,
author = {Gengjie Chen and
Chak{-}Wa Pui and
Wing{-}Kai Chow and
Ka{-}Chun Lam and
Jian Kuang and
Evangeline F. Y. Young and
Bei Yu},
title = {RippleFPGA: Routability-Driven Simultaneous Packing and Placement
for Modern FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {10},
pages = {2022--2035},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2778058},
doi = {10.1109/TCAD.2017.2778058},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenPCLKYY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenPIZZS18,
author = {Shaoming Chen and
Lu Peng and
Samuel Irving and
Zhou Zhao and
Weihua Zhang and
Ashok Srivastava},
title = {qSwitch: Dynamical Off-Chip Bandwidth Allocation Between Local and
Remote Accesses},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {1},
pages = {75--87},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2705154},
doi = {10.1109/TCAD.2017.2705154},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ChenPIZZS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenPY18,
author = {Pai{-}Yu Chen and
Xiaochen Peng and
Shimeng Yu},
title = {NeuroSim: {A} Circuit-Level Macro Model for Benchmarking Neuro-Inspired
Architectures in Online Learning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {12},
pages = {3067--3080},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2789723},
doi = {10.1109/TCAD.2018.2789723},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenPY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenSM18,
author = {Zhuo Chen and
Dimitrios Stamoulis and
Diana Marculescu},
title = {Profit: Priority and Power/Performance Optimization for Many-Core
Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {10},
pages = {2064--2075},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2772822},
doi = {10.1109/TCAD.2017.2772822},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenSM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChengLWSLL18,
author = {Yun Cheng and
Huawei Li and
Ying Wang and
Haihua Shen and
Bo Liu and
Xiaowei Li},
title = {On Trace Buffer Reuse-Based Trigger Generation in Post-Silicon Debug},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {10},
pages = {2166--2179},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2778084},
doi = {10.1109/TCAD.2017.2778084},
timestamp = {Thu, 11 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChengLWSLL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChengMSCCSSLABM18,
author = {Eric Cheng and
Shahrzad Mirkhani and
Lukasz G. Szafaryn and
Chen{-}Yong Cher and
Hyungmin Cho and
Kevin Skadron and
Mircea R. Stan and
Klas Lilja and
Jacob A. Abraham and
Pradip Bose and
Subhasish Mitra},
title = {Tolerating Soft Errors in Processor Cores Using {CLEAR} (Cross-Layer
Exploration for Architecting Resilience)},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {9},
pages = {1839--1852},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2752705},
doi = {10.1109/TCAD.2017.2752705},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ChengMSCCSSLABM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChengWE18,
author = {Zhuoqun Cheng and
Richard West and
Craig Einstein},
title = {End-to-End Analysis and Design of a Drone Flight Controller},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2404--2415},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857399},
doi = {10.1109/TCAD.2018.2857399},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChengWE18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChouCWC18,
author = {Chung{-}Han Chou and
Tsui{-}Yun Chang and
Kai{-}Chiang Wu and
Shih{-}Chieh Chang},
title = {Sensor-Based Time Speculation in the Presence of Timing Variability},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {6},
pages = {1133--1142},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2748028},
doi = {10.1109/TCAD.2017.2748028},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChouCWC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChouSYRNO18,
author = {Glen Chou and
Yunus Emre Sahin and
Liren Yang and
Kwesi J. Rutledge and
Petter Nilsson and
Necmiye Ozay},
title = {Using Control Synthesis to Generate Corner Cases: {A} Case Study on
Autonomous Driving},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2906--2917},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2858464},
doi = {10.1109/TCAD.2018.2858464},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChouSYRNO18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CiriglianoCNS18,
author = {Andrea Cirigliano and
Roberto Cordone and
Alessandro Antonio Nacci and
Marco Domenico Santambrogio},
title = {Toward Smart Building Design Automation: Extensible {CAD} Framework
for Indoor Localization Systems Deployment},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {1},
pages = {133--145},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2016.2638448},
doi = {10.1109/TCAD.2016.2638448},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CiriglianoCNS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ContiSB18,
author = {Francesco Conti and
Pasquale Davide Schiavone and
Luca Benini},
title = {{XNOR} Neural Engine: {A} Hardware Accelerator {IP} for 21.6-fJ/op
Binary Neural Network Inference},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2940--2951},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857019},
doi = {10.1109/TCAD.2018.2857019},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ContiSB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CostaFD18,
author = {Antonio Anastasio Bruto da Costa and
Goran Frehse and
Pallab Dasgupta},
title = {Formal Feature Interpretation of Hybrid Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2474--2484},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857361},
doi = {10.1109/TCAD.2018.2857361},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/CostaFD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CuiZSXWY18,
author = {Jinhua Cui and
Youtao Zhang and
Liang Shi and
Chun Jason Xue and
Weiguo Wu and
Jun Yang},
title = {ApproxFTL: On the Performance and Lifetime Improvement of 3-D {NAND}
Flash-Based SSDs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {10},
pages = {1957--1970},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2782765},
doi = {10.1109/TCAD.2017.2782765},
timestamp = {Fri, 21 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CuiZSXWY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CuiZWYWH18,
author = {Jinhua Cui and
Youtao Zhang and
Weiguo Wu and
Jun Yang and
Yinfeng Wang and
Jianhang Huang},
title = {{DLV:} Exploiting Device Level Latency Variations for Performance
Improvement on Flash Memory Storage Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {8},
pages = {1546--1559},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2766156},
doi = {10.1109/TCAD.2017.2766156},
timestamp = {Fri, 21 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CuiZWYWH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DaboulHHS18,
author = {Siad Daboul and
Nicolai H{\"{a}}hnle and
Stephan Held and
Ulrike Schorr},
title = {Provably Fast and Near-Optimum Gate Sizing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {12},
pages = {3163--3176},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2801231},
doi = {10.1109/TCAD.2018.2801231},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DaboulHHS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DamschenMH18,
author = {Marvin Damschen and
Frank Mueller and
J{\"{o}}rg Henkel},
title = {Co-Scheduling on Fused {CPU-GPU} Architectures With Shared Last Level
Caches},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2337--2347},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857042},
doi = {10.1109/TCAD.2018.2857042},
timestamp = {Mon, 22 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/DamschenMH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DaoLM18,
author = {Ai Quoc Dao and
Mark Po{-}Hung Lin and
Alan Mishchenko},
title = {SAT-Based Fault Equivalence Checking in Functional Safety Verification},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {12},
pages = {3198--3205},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2791465},
doi = {10.1109/TCAD.2018.2791465},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DaoLM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DemirH18,
author = {Alper Demir and
M. Selim Hanay},
title = {Numerical Analysis of Multidomain Systems: Coupled Nonlinear PDEs
and DAEs With Noise},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {7},
pages = {1445--1458},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2753699},
doi = {10.1109/TCAD.2017.2753699},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DemirH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DingCM18,
author = {Yixiao Ding and
Chris Chu and
Wai{-}Kei Mak},
title = {Self-Aligned Double Patterning-Aware Detailed Routing With Double
Via Insertion and Via Manufacturability Consideration},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {3},
pages = {657--668},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2712660},
doi = {10.1109/TCAD.2017.2712660},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DingCM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DobreKL18,
author = {Sorin Dobre and
Andrew B. Kahng and
Jiajia Li},
title = {Design Implementation With Noninteger Multiple-Height Cells for Improved
Design Quality in Advanced Nodes},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {4},
pages = {855--868},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2731679},
doi = {10.1109/TCAD.2017.2731679},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DobreKL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DofeY18,
author = {Jaya Dofe and
Qiaoyan Yu},
title = {Novel Dynamic State-Deflection Method for Gate-Level Design Obfuscation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {2},
pages = {273--285},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2697960},
doi = {10.1109/TCAD.2017.2697960},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DofeY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DonatoBPZ18,
author = {Marco Donato and
R. Iris Bahar and
William R. Patterson and
Alexander Zaslavsky},
title = {A Sub-Threshold Noise Transient Simulator Based on Integrated Random
Telegraph and Thermal Noise Modeling},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {3},
pages = {643--656},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2717705},
doi = {10.1109/TCAD.2017.2717705},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/DonatoBPZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DuLZLDKC18,
author = {Li Du and
Chun{-}Chen Liu and
Yan Zhang and
Yilei Li and
Yuan Du and
Yen{-}Cheng Kuan and
Mau{-}Chung Frank Chang},
title = {A Single Layer 3-D Touch Sensing System for Mobile Devices Application},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {2},
pages = {286--296},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2702630},
doi = {10.1109/TCAD.2017.2702630},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DuLZLDKC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/EhsanAZY18,
author = {M. Amimul Ehsan and
Hongyu An and
Zhen Zhou and
Yang Yi},
title = {A Novel Approach for Using TSVs As Membrane Capacitance in Neuromorphic
3-D {IC}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {8},
pages = {1640--1653},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2760506},
doi = {10.1109/TCAD.2017.2760506},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/EhsanAZY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FeldS18,
author = {Timo Feld and
Frank Slomka},
title = {Exact Interference of Tasks With Variable Rate-Dependent Behavior},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {5},
pages = {954--967},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2729459},
doi = {10.1109/TCAD.2017.2729459},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FeldS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FirouziFIC18,
author = {Farshad Firouzi and
Bahar J. Farahani and
Mohamed Ibrahim and
Krishnendu Chakrabarty},
title = {Keynote Paper: From {EDA} to IoT eHealth: Promises, Challenges, and
Solutions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {12},
pages = {2965--2978},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2801227},
doi = {10.1109/TCAD.2018.2801227},
timestamp = {Tue, 31 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FirouziFIC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FuWLXZH18,
author = {Chenchen Fu and
Peng Wu and
Minming Li and
Chun Jason Xue and
Yingchao Zhao and
Song Han},
title = {Real-Time Data Retrieval With Multiple Availability Intervals in {CPS}
Under Freshness Constraints},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2743--2754},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857378},
doi = {10.1109/TCAD.2018.2857378},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FuWLXZH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GaoMAAR18,
author = {Yansong Gao and
Hua Ma and
Said F. Al{-}Sarawi and
Derek Abbott and
Damith Chinthana Ranasinghe},
title = {{PUF-FSM:} {A} Controlled Strong {PUF}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {5},
pages = {1104--1108},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2740297},
doi = {10.1109/TCAD.2017.2740297},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GaoMAAR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GaoSJDWXS18,
author = {Congming Gao and
Liang Shi and
Cheng Ji and
Yejia Di and
Kaijie Wu and
Chun Jason Xue and
Edwin Hsing{-}Mean Sha},
title = {Exploiting Parallelism for Access Conflict Minimization in Flash-Based
Solid State Drives},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {1},
pages = {168--181},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2693281},
doi = {10.1109/TCAD.2017.2693281},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GaoSJDWXS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GengKKS18,
author = {Hui Geng and
Kevin A. Kwiat and
Charles A. Kamhoua and
Yiyu Shi},
title = {On Random Dynamic Voltage Scaling for Internet-of-Things: {A} Game-Theoretic
Approach},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {1},
pages = {123--132},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2717780},
doi = {10.1109/TCAD.2017.2717780},
timestamp = {Tue, 13 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/GengKKS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GeorgiouVKC18,
author = {Panagiotis Georgiou and
Fotis Vartziotis and
Xrysovalantis Kavousianos and
Krishnendu Chakrabarty},
title = {Testing 3D-SoCs Using 2-D Time-Division Multiplexing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {12},
pages = {3177--3185},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2780054},
doi = {10.1109/TCAD.2017.2780054},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/GeorgiouVKC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GholipourCC18,
author = {Morteza Gholipour and
Ying{-}Yu Chen and
Deming Chen},
title = {Compact Modeling to Device- and Circuit-Level Evaluation of Flexible
{TMD} Field-Effect Transistors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {4},
pages = {820--831},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2729460},
doi = {10.1109/TCAD.2017.2729460},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GholipourCC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GiraultPQHS18,
author = {Alain Girault and
Christophe Pr{\'{e}}vot and
Sophie Quinton and
Rafik Henia and
Nicolas Sordon},
title = {Improving and Estimating the Precision of Bounds on the Worst-Case
Latency of Task Chains},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2578--2589},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2861016},
doi = {10.1109/TCAD.2018.2861016},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GiraultPQHS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GongWLCZ18,
author = {Lei Gong and
Chao Wang and
Xi Li and
Huaping Chen and
Xuehai Zhou},
title = {{MALOC:} {A} Fully Pipelined {FPGA} Accelerator for Convolutional
Neural Networks With All Layers Mapped on Chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2601--2612},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857078},
doi = {10.1109/TCAD.2018.2857078},
timestamp = {Tue, 22 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GongWLCZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GrimmerHSW18,
author = {Andreas Grimmer and
Werner Haselmayr and
Andreas Springer and
Robert Wille},
title = {Design of Application-Specific Architectures for Networked Labs-on-Chips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {1},
pages = {193--202},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2702562},
doi = {10.1109/TCAD.2017.2702562},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GrimmerHSW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GuoSQYWYHWY18,
author = {Kaiyuan Guo and
Lingzhi Sui and
Jiantao Qiu and
Jincheng Yu and
Junbin Wang and
Song Yao and
Song Han and
Yu Wang and
Huazhong Yang},
title = {Angel-Eye: {A} Complete Design Flow for Mapping {CNN} Onto Embedded
{FPGA}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {1},
pages = {35--47},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2705069},
doi = {10.1109/TCAD.2017.2705069},
timestamp = {Fri, 20 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/GuoSQYWYHWY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Gupta18,
author = {Rajesh K. Gupta},
title = {Editorial},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {1},
pages = {1--2},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2781779},
doi = {10.1109/TCAD.2017.2781779},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Gupta18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HaE18,
author = {Soonhoi Ha and
Petru Eles},
title = {Editorial},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2187},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2872331},
doi = {10.1109/TCAD.2018.2872331},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HaE18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HanLLLP18,
author = {Kyuseung Han and
Jae{-}Jin Lee and
Jinho Lee and
Woojoo Lee and
Massoud Pedram},
title = {TEI-NoC: Optimizing Ultralow Power NoCs Exploiting the Temperature
Effect Inversion},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {2},
pages = {458--471},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2693269},
doi = {10.1109/TCAD.2017.2693269},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HanLLLP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HanTZASY18,
author = {Jian{-}Jun Han and
Xin Tao and
Dakai Zhu and
Hakan Aydin and
Zili Shao and
Laurence T. Yang},
title = {Multicore Mixed-Criticality Systems: Partitioned Scheduling and Utilization
Bound},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {1},
pages = {21--34},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2697955},
doi = {10.1109/TCAD.2017.2697955},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HanTZASY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HaqueE18,
author = {Mohammad Shihabul Haque and
Arvind Easwaran},
title = {Predictability and Performance Aware Replacement Policy {PVISAM} for
Unified Shared Caches in Real-time Multicores},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2720--2731},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857081},
doi = {10.1109/TCAD.2018.2857081},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HaqueE18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HassanP18,
author = {Mohamed Hassan and
Hiren D. Patel},
title = {MCXplore: Automating the Validation Process of {DRAM} Memory Controller
Designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {5},
pages = {1050--1063},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2705123},
doi = {10.1109/TCAD.2017.2705123},
timestamp = {Mon, 07 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/HassanP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HassanP18a,
author = {Mohamed Hassan and
Rodolfo Pellizzoni},
title = {Bounding {DRAM} Interference in {COTS} Heterogeneous MPSoCs for Mixed
Criticality Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2323--2336},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857379},
doi = {10.1109/TCAD.2018.2857379},
timestamp = {Mon, 07 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/HassanP18a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HeldMRSTV18,
author = {Stephan Held and
Dirk M{\"{u}}ller and
Daniel Rotter and
Rudolf Scheifele and
Vera Traub and
Jens Vygen},
title = {Global Routing With Timing Constraints},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {2},
pages = {406--419},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2697964},
doi = {10.1109/TCAD.2017.2697964},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HeldMRSTV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HelmsEMN18,
author = {Domenik Helms and
Reef Eilers and
Malte Metzdorf and
Wolfgang Nebel},
title = {Leakage Models for High-Level Power Estimation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {8},
pages = {1627--1639},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2760519},
doi = {10.1109/TCAD.2017.2760519},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HelmsEMN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HongJPH18,
author = {Hyesun Hong and
Hanwoong Jung and
KangKyu Park and
Soonhoi Ha},
title = {SeMo: Service-Oriented and Model-Based Software Framework for Cooperating
Robots},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2952--2963},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857339},
doi = {10.1109/TCAD.2018.2857339},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HongJPH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HongK18,
author = {Inki Hong and
Dae Hyun Kim},
title = {Analysis of Performance Benefits of Multitier Gate-Level Monolithic
3-D Integrated Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {8},
pages = {1614--1626},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2768427},
doi = {10.1109/TCAD.2017.2768427},
timestamp = {Tue, 29 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HongK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HsiehPC18,
author = {Tong{-}Yu Hsieh and
Yi{-}Han Peng and
Kuan{-}Chih Cheng},
title = {Structural Variance-Based Error-Tolerability Test Method for Image
Processing Applications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {2},
pages = {485--498},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2705050},
doi = {10.1109/TCAD.2017.2705050},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HsiehPC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuaM18,
author = {Wenmian Hua and
Rajit Manohar},
title = {Exact Timing Analysis for Asynchronous Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {1},
pages = {203--216},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2693268},
doi = {10.1109/TCAD.2017.2693268},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuaM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuangCCB18,
author = {Hsin{-}Ho Huang and
Huimei Cheng and
Chris Chu and
Peter A. Beerel},
title = {Area Optimization of Timing Resilient Designs Using Resynthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {6},
pages = {1197--1210},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2748001},
doi = {10.1109/TCAD.2017.2748001},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuangCCB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuangLLYCCCCB18,
author = {Chau{-}Chin Huang and
Hsin{-}Ying Lee and
Bo{-}Qiao Lin and
Sheng{-}Wei Yang and
Chin{-}Hao Chang and
Szu{-}To Chen and
Yao{-}Wen Chang and
Tung{-}Chieh Chen and
Ismail Bustany},
title = {NTUplace4dr: {A} Detailed-Routing-Driven Placer for Mixed-Size Circuit
Designs With Technology and Region Constraints},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {3},
pages = {669--681},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2712665},
doi = {10.1109/TCAD.2017.2712665},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuangLLYCCCCB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HusseinJ18,
author = {Ahmed S. Hussein and
Anwar Jarndal},
title = {Reliable Hybrid Small-Signal Modeling of GaN HEMTs Based on Particle-Swarm-Optimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {9},
pages = {1816--1824},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2782779},
doi = {10.1109/TCAD.2017.2782779},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HusseinJ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/IranfarKAPA18,
author = {Arman Iranfar and
Mehdi Kamal and
Ali Afzali{-}Kusha and
Massoud Pedram and
David Atienza},
title = {TheSPoT: Thermal Stress-Aware Power and Temperature Management for
Multiprocessor Systems-on-Chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {8},
pages = {1532--1545},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2768417},
doi = {10.1109/TCAD.2017.2768417},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/IranfarKAPA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JaksicBGN18,
author = {Stefan Jaksic and
Ezio Bartocci and
Radu Grosu and
Dejan Nickovic},
title = {An Algebraic Framework for Runtime Verification},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2233--2243},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2858460},
doi = {10.1109/TCAD.2018.2858460},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JaksicBGN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JayakodiCCDP18,
author = {Nitthilan Kannappan Jayakodi and
Anwesha Chatterjee and
Wonje Choi and
Janardhan Rao Doppa and
Partha Pratim Pande},
title = {Trading-Off Accuracy and Energy of Deep Inference on Embedded Systems:
{A} Co-Design Approach},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2881--2893},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857338},
doi = {10.1109/TCAD.2018.2857338},
timestamp = {Fri, 12 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JayakodiCCDP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JiCWSX18,
author = {Cheng Ji and
Li{-}Pin Chang and
Chao Wu and
Liang Shi and
Chun Jason Xue},
title = {An {I/O} Scheduling Strategy for Embedded Flash Storage Devices With
Mapping Cache},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {4},
pages = {756--769},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2729405},
doi = {10.1109/TCAD.2017.2729405},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JiCWSX18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JiaCZY18,
author = {Xiaotao Jia and
Yici Cai and
Qiang Zhou and
Bei Yu},
title = {A Multicommodity Flow-Based Detailed Router With Efficient Acceleration
Techniques},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {1},
pages = {217--230},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2693270},
doi = {10.1109/TCAD.2017.2693270},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JiaCZY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JiangLJKGL18,
author = {Li Jiang and
Tianjian Li and
Naifeng Jing and
Nam Sung Kim and
Minyi Guo and
Xiaoyao Liang},
title = {CNFET-Based High Throughput {SIMD} Architecture},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {7},
pages = {1331--1344},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2695899},
doi = {10.1109/TCAD.2017.2695899},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JiangLJKGL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JiangSZYCH18,
author = {Weiwen Jiang and
Edwin Hsing{-}Mean Sha and
Qingfeng Zhuge and
Lei Yang and
Xianzhang Chen and
Jingtong Hu},
title = {Heterogeneous FPGA-Based Cost-Optimal Design for Timing-Constrained
CNNs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2542--2554},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857098},
doi = {10.1109/TCAD.2018.2857098},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JiangSZYCH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JiaoLD18,
author = {Fanshu Jiao and
Hao Li and
Alex Doboli},
title = {Modeling and Extraction of Causal Information in Analog Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {10},
pages = {1915--1928},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2783359},
doi = {10.1109/TCAD.2017.2783359},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JiaoLD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JinZCG18,
author = {Shi Jin and
Zhaobo Zhang and
Krishnendu Chakrabarty and
Xinli Gu},
title = {Toward Predictive Fault Tolerance in a Core-Router System: Anomaly
Detection Using Correlation-Based Time-Series Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {10},
pages = {2111--2124},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2775240},
doi = {10.1109/TCAD.2017.2775240},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/JinZCG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JuSLZXHJ18,
author = {Lei Ju and
Xiaojin Sui and
Shiqing Li and
Mengying Zhao and
Chun Jason Xue and
Jingtong Hu and
Zhiping Jia},
title = {NVM-Based {FPGA} Block {RAM} With Adaptive {SLC-MLC} Conversion},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2661--2672},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857261},
doi = {10.1109/TCAD.2018.2857261},
timestamp = {Tue, 07 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/JuSLZXHJ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JungNRJS18,
author = {Jinwook Jung and
Gi{-}Joon Nam and
Lakshmi N. Reddy and
Iris Hui{-}Ru Jiang and
Youngsoo Shin},
title = {{OWARU:} Free Space-Aware Timing-Driven Incremental Placement With
Critical Path Smoothing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {9},
pages = {1825--1838},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2774277},
doi = {10.1109/TCAD.2017.2774277},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JungNRJS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KahngKLL18,
author = {Alex Kahng and
Andrew B. Kahng and
Hyein Lee and
Jiajia Li},
title = {{PROBE:} {A} Placement, Routing, Back-End-of-Line Measurement Utility},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {7},
pages = {1459--1472},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2750072},
doi = {10.1109/TCAD.2017.2750072},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KahngKLL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KermaniJAXC18,
author = {Mehran Mozaffari Kermani and
Amir Jalali and
Reza Azarderakhsh and
Jiafeng Xie and
Kim{-}Kwang Raymond Choo},
title = {Reliable Inversion in GF(2\({}^{\mbox{8}}\)) With Redundant Arithmetic
for Secure Error Detection of Cryptographic Architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {3},
pages = {696--704},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2717791},
doi = {10.1109/TCAD.2017.2717791},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KermaniJAXC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimKEL18,
author = {Jin Hyun Kim and
Kyong Hoon Kim and
Arvind Easwaran and
Insup Lee},
title = {Towards Overhead-Free Interface Theory for Compositional Hierarchical
Real-Time Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2869--2880},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2858465},
doi = {10.1109/TCAD.2018.2858465},
timestamp = {Thu, 26 Jan 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/KimKEL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimNYM18,
author = {Duckhwan Kim and
Taesik Na and
Sudhakar Yalamanchili and
Saibal Mukhopadhyay},
title = {DeepTrain: {A} Programmable Embedded Platform for Training Deep Neural
Networks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2360--2370},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2858358},
doi = {10.1109/TCAD.2018.2858358},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KimNYM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KoleDS18,
author = {Abhoy Kole and
Kamalika Datta and
Indranil Sengupta},
title = {A New Heuristic for N-Dimensional Nearest Neighbor Realization of
a Quantum Circuit},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {1},
pages = {182--192},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2693284},
doi = {10.1109/TCAD.2017.2693284},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KoleDS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KrestinskayaIJ18,
author = {Olga Krestinskaya and
Timur Ibrayev and
Alex Pappachen James},
title = {Hierarchical Temporal Memory Features with Memristor Logic Circuits
for Pattern Recognition},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {6},
pages = {1143--1156},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2748024},
doi = {10.1109/TCAD.2017.2748024},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KrestinskayaIJ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KuangYY18,
author = {Jian Kuang and
Junjie Ye and
Evangeline F. Y. Young},
title = {{STOMA:} Simultaneous Template Optimization and Mask Assignment for
Directed Self-Assembly Lithography With Multiple Patterning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {6},
pages = {1251--1264},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2748022},
doi = {10.1109/TCAD.2017.2748022},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KuangYY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KuangYY18a,
author = {Jian Kuang and
Evangeline F. Y. Young and
Bei Yu},
title = {{CRMA:} Incorporating Cut Redistribution With Mask Assignment to Enable
the Fabrication of 1-D Gridded Design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {10},
pages = {2036--2049},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2778069},
doi = {10.1109/TCAD.2017.2778069},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KuangYY18a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KumarTM18,
author = {S. Dinesh Kumar and
Himanshu Thapliyal and
Azhar Mohammad},
title = {FinSAL: FinFET-Based Secure Adiabatic Logic for Energy-Efficient and
{DPA} Resistant IoT Devices},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {1},
pages = {110--122},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2685588},
doi = {10.1109/TCAD.2017.2685588},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KumarTM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LadenheimCMP18,
author = {Scott Ladenheim and
Yi{-}Chung Chen and
Milan Mihajlovic and
Vasilis F. Pavlidis},
title = {The {MTA:} An Advanced and Versatile Thermal Simulator for Integrated
Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {12},
pages = {3123--3136},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2789729},
doi = {10.1109/TCAD.2018.2789729},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LadenheimCMP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LahiouelZT18,
author = {Ons Lahiouel and
Mohamed H. Zaki and
Sofi{\`{e}}ne Tahar},
title = {Accelerated and Reliable Analog Circuits Yield Analysis Using {SMT}
Solving Techniques},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {3},
pages = {517--530},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2651807},
doi = {10.1109/TCAD.2017.2651807},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LahiouelZT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeAPSCO18,
author = {Vincent T. Lee and
Armin Alaghi and
Rajesh Pamula and
Visvesh S. Sathe and
Luis Ceze and
Mark Oskin},
title = {Architecture Considerations for Stochastic Computing Accelerators},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2277--2289},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2858338},
doi = {10.1109/TCAD.2018.2858338},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeAPSCO18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeCKK18,
author = {Hayoung Lee and
Kiwon Cho and
Donghyun Kim and
Sungho Kang},
title = {Fault Group Pattern Matching With Efficient Early Termination for
High-Speed Redundancy Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {7},
pages = {1473--1482},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2760505},
doi = {10.1109/TCAD.2017.2760505},
timestamp = {Tue, 27 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LeeCKK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeCSW18,
author = {Youngmoon Lee and
Hoon Sung Chwa and
Kang G. Shin and
Shige Wang},
title = {Thermal-Aware Resource Management for Embedded Real-Time Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2857--2868},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857279},
doi = {10.1109/TCAD.2018.2857279},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeCSW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeKC18,
author = {Byunghoon Lee and
Kwangsu Kim and
Eui{-}Young Chung},
title = {Replacement Policy Adaptable Miss Curve Estimation for Efficient Cache
Partitioning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {2},
pages = {445--457},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2712666},
doi = {10.1109/TCAD.2017.2712666},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeKC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeKH18,
author = {Jae Hoon Lee and
Min Soo Kim and
Tae Hee Han},
title = {Insertion Loss-Aware Routing Analysis and Optimization for a Fat-Tree-Based
Optical Network-on-Chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {3},
pages = {559--572},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2712670},
doi = {10.1109/TCAD.2017.2712670},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeKH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeePY18,
author = {Taehee Lee and
David Z. Pan and
Joon{-}Sung Yang},
title = {Clock Network Optimization With Multibit Flip-Flop Generation Considering
Multicorner Multimode Timing Constraint},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {1},
pages = {245--256},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2698025},
doi = {10.1109/TCAD.2017.2698025},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeePY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiDP18,
author = {Wuxi Li and
Shounak Dhar and
David Z. Pan},
title = {UTPlaceF: {A} Routability-Driven {FPGA} Placer With Physical and Congestion
Aware Packing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {4},
pages = {869--882},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2729349},
doi = {10.1109/TCAD.2017.2729349},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiDP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiDWDDTSIC18,
author = {Yilei Li and
Kirti Dhwaj and
Chien{-}Heng Wong and
Yuan Du and
Li Du and
Yiwu Tang and
Yiyu Shi and
Tatsuo Itoh and
Mau{-}Chung Frank Chang},
title = {A Novel Fully Synthesizable All-Digital {RF} Transmitter for IoT Applications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {1},
pages = {146--158},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2684097},
doi = {10.1109/TCAD.2017.2684097},
timestamp = {Tue, 13 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LiDWDDTSIC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiL18,
author = {Tao Li and
Qiang Liu},
title = {A Low Cost Partial Scan Approach Based on Balanced Sequential Graph
Transformation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {5},
pages = {1109--1113},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2729348},
doi = {10.1109/TCAD.2017.2729348},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiLJDD18,
author = {Hao Li and
Xiaowei Liu and
Fanshu Jiao and
Alex Doboli and
Simona Doboli},
title = {InnovA: {A} Cognitive Architecture for Computational Innovation Through
Robust Divergence and Its Application for Analog Circuit Design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {10},
pages = {1943--1956},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2783344},
doi = {10.1109/TCAD.2017.2783344},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiLJDD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiLMYCPHL18,
author = {Zipeng Li and
Kelvin Yi{-}Tse Lai and
John McCrone and
Po{-}Hsien Yu and
Krishnendu Chakrabarty and
Miroslav Pajic and
Tsung{-}Yi Ho and
Chen{-}Yi Lee},
title = {Efficient and Adaptive Error Recovery in a Micro-Electrode-Dot-Array
Digital Microfluidic Biochip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {3},
pages = {601--614},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2729347},
doi = {10.1109/TCAD.2017.2729347},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LiLMYCPHL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiLYCC18,
author = {Mengquan Li and
Weichen Liu and
Lei Yang and
Peng Chen and
Chao Chen},
title = {Chip Temperature Optimization for Dark Silicon Many-Core Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {5},
pages = {941--953},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2740306},
doi = {10.1109/TCAD.2017.2740306},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiLYCC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiLYCHL18,
author = {Zipeng Li and
Kelvin Yi{-}Tse Lai and
Po{-}Hsien Yu and
Krishnendu Chakrabarty and
Tsung{-}Yi Ho and
Chen{-}Yi Lee},
title = {Structural and Functional Test Methods for Micro-Electrode-Dot-Array
Digital Microfluidic Biochips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {5},
pages = {968--981},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2740299},
doi = {10.1109/TCAD.2017.2740299},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LiLYCHL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiXWMYT18,
author = {Haoran Li and
Jiang Xu and
Zhe Wang and
Rafael K. V. Maeda and
Peng Yang and
Zhongyuan Tian},
title = {Workload-Aware Adaptive Power Delivery System Management for Many-Core
Processors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {10},
pages = {2076--2086},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2778080},
doi = {10.1109/TCAD.2017.2778080},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiXWMYT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiangSZ18,
author = {Hao Liang and
Sharad Sinha and
Wei Zhang},
title = {Parallelizing Hardware Tasks on Multicontext {FPGA} With Efficient
Placement and Scheduling Algorithms},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {2},
pages = {350--363},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2697952},
doi = {10.1109/TCAD.2017.2697952},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiangSZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiangXWSW18,
author = {Yun Liang and
Xiaolong Xie and
Yu Wang and
Guangyu Sun and
Tao Wang},
title = {Optimizing Cache Bypassing and Warp Scheduling for GPUs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {8},
pages = {1560--1573},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2764886},
doi = {10.1109/TCAD.2017.2764886},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiangXWSW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiangZFSZ18,
author = {Tingyuan Liang and
Jieru Zhao and
Liang Feng and
Sharad Sinha and
Wei Zhang},
title = {Hi-DMM: High-Performance Dynamic Memory Management in High-Level Synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2555--2566},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857040},
doi = {10.1109/TCAD.2018.2857040},
timestamp = {Tue, 05 Mar 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LiangZFSZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LimOKK18,
author = {Jaeil Lim and
Hyunggoy Oh and
Heetae Kim and
Sungho Kang},
title = {Thermal Aware Test Scheduling for {NTV} Circuit},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {4},
pages = {906--910},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2729282},
doi = {10.1109/TCAD.2017.2729282},
timestamp = {Tue, 27 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LimOKK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinK18,
author = {Sheng{-}En David Lin and
Dae Hyun Kim},
title = {Detailed-Placement-Enabled Dynamic Power Optimization of Multitier
Gate-Level Monolithic 3-D ICs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {4},
pages = {845--854},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2729401},
doi = {10.1109/TCAD.2017.2729401},
timestamp = {Tue, 29 Jun 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinTLYLHCKLC18,
author = {Chien{-}Hsueh Lin and
Chih{-}Ying Tsai and
Kao{-}Chi Lee and
Sung{-}Chu Yu and
Wen{-}Rong Liau and
Alex Chun{-}Liang Hou and
Ying{-}Yen Chen and
Chun{-}Yi Kuo and
Jih{-}Nung Lee and
Mango C.{-}T. Chao},
title = {A Model-Based-Random-Forest Framework for Predicting V\({}_{\mbox{t}}\)
Mean and Variance Based on Parallel I\({}_{\mbox{d}}\) Measurement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {10},
pages = {2139--2151},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2783304},
doi = {10.1109/TCAD.2017.2783304},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinTLYLHCKLC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinYLP18,
author = {Yibo Lin and
Bei Yu and
Meng Li and
David Z. Pan},
title = {Layout Synthesis for Topological Quantum Circuits With 1-D and 2-D
Architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {8},
pages = {1574--1587},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2760511},
doi = {10.1109/TCAD.2017.2760511},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinYLP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinYXGVLLAP18,
author = {Yibo Lin and
Bei Yu and
Xiaoqing Xu and
Jhih{-}Rong Gao and
Natarajan Viswanathan and
Wen{-}Hao Liu and
Zhuo Li and
Charles J. Alpert and
David Z. Pan},
title = {MrDP: Multiple-Row Detailed Placement of Heterogeneous-Sized Cells
for Advanced Nodes},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {6},
pages = {1237--1250},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2748025},
doi = {10.1109/TCAD.2017.2748025},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinYXGVLLAP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuCR18,
author = {Jiangchao Liu and
Liqian Chen and
Xavier Rival},
title = {Automatic Verification of Embedded System Code Manipulating Dynamic
Structures Stored in Contiguous Regions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2311--2322},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2858462},
doi = {10.1109/TCAD.2018.2858462},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuCR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuHH18,
author = {Lin Liu and
Hui Huang and
Shiyan Hu},
title = {Lorenz Chaotic System-Based Carbon Nanotube Physical Unclonable Functions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {7},
pages = {1408--1421},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2762919},
doi = {10.1109/TCAD.2017.2762919},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuHH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuJLH18,
author = {Siting Liu and
Honglan Jiang and
Leibo Liu and
Jie Han},
title = {Gradient Descent Using Stochastic Circuits for Efficient Training
of Learning Machines},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2530--2541},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2858363},
doi = {10.1109/TCAD.2018.2858363},
timestamp = {Mon, 08 Jan 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LiuJLH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuMLWWCLWPG18,
author = {Zihao Liu and
Mengjie Mao and
Tao Liu and
Xue Wang and
Wujie Wen and
Yiran Chen and
Hai Li and
Danghui Wang and
Yukui Pei and
Ning Ge},
title = {TriZone: {A} Design of {MLC} {STT-RAM} Cache for Combined Performance,
Energy, and Reliability Optimizations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {10},
pages = {1985--1998},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2783860},
doi = {10.1109/TCAD.2017.2783860},
timestamp = {Mon, 04 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuMLWWCLWPG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuWBC18,
author = {Junyi Liu and
John Wickerson and
Samuel Bayliss and
George A. Constantinides},
title = {Polyhedral-Based Dynamic Loop Pipelining for High-Level Synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {9},
pages = {1802--1815},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2783363},
doi = {10.1109/TCAD.2017.2783363},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuWBC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuWDZYW18,
author = {Leibo Liu and
Bo Wang and
Chenchen Deng and
Min Zhu and
Shouyi Yin and
Shaojun Wei},
title = {Anole: {A} Highly Efficient Dynamically Reconfigurable Crypto-Processor
for Symmetric-Key Algorithms},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {12},
pages = {3081--3094},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2801229},
doi = {10.1109/TCAD.2018.2801229},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuWDZYW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuYCP18,
author = {Derong Liu and
Bei Yu and
Salim Chowdhury and
David Z. Pan},
title = {{TILA-S:} Timing-Driven Incremental Layer Assignment Avoiding Slew
Violations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {1},
pages = {231--244},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2652221},
doi = {10.1109/TCAD.2017.2652221},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuYCP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuYYW18,
author = {Leibo Liu and
Chen Yang and
Shouyi Yin and
Shaojun Wei},
title = {{CDPM:} Context-Directed Pattern Matching Prefetching to Improve Coarse-Grained
Reconfigurable Array Performance},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {6},
pages = {1171--1184},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2748026},
doi = {10.1109/TCAD.2017.2748026},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuYYW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuZH18,
author = {Yang Liu and
Yuchen Zhou and
Shiyan Hu},
title = {Combating Coordinated Pricing Cyberattack and Energy Theft in Smart
Home Cyber-Physical Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {3},
pages = {573--586},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2717781},
doi = {10.1109/TCAD.2017.2717781},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuZH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuZWZYM18,
author = {Leibo Liu and
Zhuoquan Zhou and
Shaojun Wei and
Min Zhu and
Shouyi Yin and
Shengyang Mao},
title = {DRMaSV: Enhanced Capability Against Hardware Trojans in Coarse Grained
Reconfigurable Architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {4},
pages = {782--795},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2729340},
doi = {10.1109/TCAD.2017.2729340},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuZWZYM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LoharDPG18,
author = {Debasmita Lohar and
Eva Darulova and
Sylvie Putot and
Eric Goubault},
title = {Discrete Choice in the Presence of Numerical Uncertainties},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2381--2392},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857320},
doi = {10.1109/TCAD.2018.2857320},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LoharDPG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LongLS18,
author = {Yanchen Long and
Zhonghai Lu and
Haibin Shen},
title = {Composable Worst-Case Delay Bound Analysis Using Network Calculus},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {3},
pages = {705--709},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2729283},
doi = {10.1109/TCAD.2017.2729283},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LongLS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LoraVFQF18,
author = {Michele Lora and
Sara Vinco and
Enrico Fraccaroli and
Davide Quaglia and
Franco Fummi},
title = {Analog Models Manipulation for Effective Integration in Smart System
Virtual Platforms},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {2},
pages = {378--391},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2705129},
doi = {10.1109/TCAD.2017.2705129},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LoraVFQF18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LuC18,
author = {Liang{-}Ying Lu and
Lih{-}Yih Chiou},
title = {Temperature Gradient Exploration Method for Determining the Appropriate
Number of Cells in Mesh-Based Thermal Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {12},
pages = {3216--3220},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2801225},
doi = {10.1109/TCAD.2018.2801225},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LuC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LuZ18,
author = {Zhonghai Lu and
Xueqian Zhao},
title = {xMAS-Based QoS Analysis Methodology},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {2},
pages = {364--377},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2706561},
doi = {10.1109/TCAD.2017.2706561},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LuZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LubanaD18,
author = {Ekdeep Singh Lubana and
Robert P. Dick},
title = {Digital Foveation: An Energy-Aware Machine Vision Framework},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2371--2380},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2858340},
doi = {10.1109/TCAD.2018.2858340},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LubanaD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaffezzoniD18,
author = {Paolo Maffezzoni and
Luca Daniel},
title = {Exploiting Oscillator Arrays As Randomness Sources for Cryptographic
Applications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {12},
pages = {2999--3007},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2783298},
doi = {10.1109/TCAD.2017.2783298},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MaffezzoniD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaffezzoniZLD18,
author = {Paolo Maffezzoni and
Zheng Zhang and
Salvatore Levantino and
Luca Daniel},
title = {Variation-Aware Modeling of Integrated Capacitors Based on Floating
Random Walk Extraction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {10},
pages = {2180--2184},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2789730},
doi = {10.1109/TCAD.2018.2789730},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MaffezzoniZLD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaoHAMTMSK18,
author = {Baolei Mao and
Wei Hu and
Alric Althoff and
Janarbek Matai and
Yu Tai and
Dejun Mu and
Timothy Sherwood and
Ryan Kastner},
title = {Quantitative Analysis of Timing Channel Security in Cryptographic
Hardware Design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {9},
pages = {1719--1732},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2768420},
doi = {10.1109/TCAD.2017.2768420},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MaoHAMTMSK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaoWD18,
author = {Bo Mao and
Suzhen Wu and
Lide Duan},
title = {Improving the {SSD} Performance by Exploiting Request Characteristics
and Internal Parallelism},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {2},
pages = {472--484},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2697961},
doi = {10.1109/TCAD.2017.2697961},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MaoWD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MappourasVCS18,
author = {Georgios Mappouras and
Alireza Vahid and
A. Robert Calderbank and
Daniel J. Sorin},
title = {Extending Flash Lifetime in Embedded Processors by Expanding Analog
Choice},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2462--2473},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857059},
doi = {10.1109/TCAD.2018.2857059},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MappourasVCS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MarchandBMBCF18,
author = {C{\'{e}}dric Marchand and
Lilian Bossuet and
Ugo Mureddu and
Nathalie Bochard and
Abdelkarim Cherkaoui and
Viktor Fischer},
title = {Implementation and Characterization of a Physical Unclonable Function
for IoT: {A} Case Study With the {TERO-PUF}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {1},
pages = {97--109},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2702607},
doi = {10.1109/TCAD.2017.2702607},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/MarchandBMBCF18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MartinezOB18,
author = {Jorge Martinez and
Ignacio Sanudo Olmedo and
Marko Bertogna},
title = {Analytical Characterization of End-to-End Communication Delays With
Logical Execution Time},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2244--2254},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857398},
doi = {10.1109/TCAD.2018.2857398},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MartinezOB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MengXY18,
author = {Fanruo Meng and
Yuan Xue and
Chengmo Yang},
title = {Power- and Endurance-Aware Neural Network Training in NVM-Based Platforms},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2709--2719},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2858360},
doi = {10.1109/TCAD.2018.2858360},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MengXY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MessarisSSKNP18,
author = {Ioannis Messaris and
Alexander Serb and
Spyros Stathopoulos and
Ali Khiat and
Spyridon Nikolaidis and
Themistoklis Prodromakis},
title = {A Data-Driven Verilog-A ReRAM Model},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {12},
pages = {3151--3162},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2791468},
doi = {10.1109/TCAD.2018.2791468},
timestamp = {Tue, 04 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MessarisSSKNP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MiaoLRMY18,
author = {Jin Miao and
Meng Li and
Subhendu Roy and
Yuzhe Ma and
Bei Yu},
title = {{SD-PUF:} Spliced Digital Physical Unclonable Function},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {5},
pages = {927--940},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2740296},
doi = {10.1109/TCAD.2017.2740296},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MiaoLRMY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MiedlHMBT18,
author = {Philipp Miedl and
Xiaoxi He and
Matthias Meyer and
Davide Basilio Bartolini and
Lothar Thiele},
title = {Frequency Scaling As a Security Threat on Multicore Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2497--2508},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857038},
doi = {10.1109/TCAD.2018.2857038},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MiedlHMBT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MinhassMRBPM18,
author = {Wajid Hassan Minhass and
Jeffrey McDaniel and
Michael Lander Raagaard and
Philip Brisk and
Paul Pop and
Jan Madsen},
title = {Scheduling and Fluid Routing for Flow-Based Microfluidic Laboratories-on-a-Chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {3},
pages = {615--628},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2729463},
doi = {10.1109/TCAD.2017.2729463},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/MinhassMRBPM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MoKS18,
author = {Lei Mo and
Angeliki Kritikakou and
Olivier Sentieys},
title = {Energy-Quality-Time Optimized Task Mapping on DVFS-Enabled Multicores},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2428--2439},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857300},
doi = {10.1109/TCAD.2018.2857300},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MoKS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MohantyHXLL18,
author = {Saraju P. Mohanty and
Michael H{\"{u}}bner and
Chun Jason Xue and
Xin Li and
Hai Li},
title = {Guest Editorial Circuit and System Design Automation for Internet
of Things},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {1},
pages = {3--6},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2779960},
doi = {10.1109/TCAD.2017.2779960},
timestamp = {Wed, 28 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MohantyHXLL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MollerKGZ18,
author = {Konrad M{\"{o}}ller and
Martin Kumm and
Mario Garrido and
Peter Zipf},
title = {Optimal Shift Reassignment in Reconfigurable Constant Multiplication
Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {3},
pages = {710--714},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2729467},
doi = {10.1109/TCAD.2017.2729467},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MollerKGZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MorePT18,
author = {Ankit More and
Vasil Pano and
Baris Taskin},
title = {Vertical Arbitration-Free 3-D NoCs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {9},
pages = {1853--1866},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2768415},
doi = {10.1109/TCAD.2017.2768415},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MorePT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MostlSE18,
author = {Mischa M{\"{o}}stl and
Johannes Schlatow and
Rolf Ernst},
title = {Synthesis of Monitors for Networked Systems With Heterogeneous Safety
Requirements},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2824--2834},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2862458},
doi = {10.1109/TCAD.2018.2862458},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MostlSE18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MukherjeeC18,
author = {Anway Mukherjee and
Thidapat Chantem},
title = {Energy Management of Applications With Varying Resource Usage on Smartphones},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2416--2427},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857323},
doi = {10.1109/TCAD.2018.2857323},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MukherjeeC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NagamaniANA18,
author = {A. N. Nagamani and
S. N. Anuktha and
N. Nanditha and
Vinod Kumar Agrawal},
title = {A Genetic Algorithm-Based Heuristic Method for Test Set Generation
in Reversible Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {2},
pages = {324--336},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2695881},
doi = {10.1109/TCAD.2017.2695881},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NagamaniANA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NairBGOHT18,
author = {Sarath Mohanachandran Nair and
Rajendra Bishnoi and
Mohammad Saber Golanbari and
Fabian Oboril and
Fazal Hameed and
Mehdi Baradaran Tahoori},
title = {{VAET-STT:} Variation Aware {STT-MRAM} Analysis and Design Space Exploration
Tool},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {7},
pages = {1396--1407},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2760861},
doi = {10.1109/TCAD.2017.2760861},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/NairBGOHT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NavarroG18,
author = {Raouf Senhadji{-}Navarro and
Ignacio Garcia{-}Vargas},
title = {High-Performance Architecture for Binary-Tree-Based Finite State Machines},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {4},
pages = {796--805},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2731678},
doi = {10.1109/TCAD.2017.2731678},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NavarroG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NeutzlingMCRR18,
author = {Augusto Neutzling and
Mayler G. A. Martins and
Vinicius Callegaro and
Andr{\'{e}} In{\'{a}}cio Reis and
Renato P. Ribas},
title = {A Simple and Effective Heuristic Method for Threshold Logic Identification},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {5},
pages = {1023--1036},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2729403},
doi = {10.1109/TCAD.2017.2729403},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NeutzlingMCRR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NiknamWS18,
author = {Sobhan Niknam and
Peng Wang and
Todor P. Stefanov},
title = {Resource Optimization for Real-Time Streaming Applications Using Task
Replication},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2755--2767},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857039},
doi = {10.1109/TCAD.2018.2857039},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NiknamWS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PahlevanQZA18,
author = {Ali Pahlevan and
Xiaoyu Qu and
Marina Zapater and
David Atienza},
title = {Integrating Heuristic and Machine-Learning Methods for Efficient Virtual
Machine Allocation in Data Centers},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {8},
pages = {1667--1680},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2760517},
doi = {10.1109/TCAD.2017.2760517},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PahlevanQZA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PajouhiR18,
author = {Zoha Pajouhi and
Kaushik Roy},
title = {Image Edge Detection Based on Swarm Intelligence Using Memristive
Networks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {9},
pages = {1774--1787},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2775227},
doi = {10.1109/TCAD.2017.2775227},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PajouhiR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PanXH18,
author = {Chen Pan and
Mimi Xie and
Jingtong Hu},
title = {{ENZYME:} An Energy-Efficient Transient Computing Paradigm for Ultralow
Self-Powered IoT Edge Devices},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2440--2450},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2858478},
doi = {10.1109/TCAD.2018.2858478},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PanXH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ParkTS18,
author = {Jea Woo Park and
Andres Torres and
Xiaoyu Song},
title = {Litho-Aware Machine Learning for Hotspot Detection},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {7},
pages = {1510--1514},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2750068},
doi = {10.1109/TCAD.2017.2750068},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ParkTS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PelcatMDMLHNHMB18,
author = {Maxime Pelcat and
Alexandre Mercat and
Karol Desnos and
Luca Maggiani and
Yanzhou Liu and
Julien Heulot and
Jean{-}Fran{\c{c}}ois Nezan and
Wassim Hamidouche and
Daniel M{\'{e}}nard and
Shuvra S. Bhattacharyya},
title = {Reproducible Evaluation of System Efficiency With a Model of Architecture:
From Theory to Practice},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {10},
pages = {2050--2063},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2774822},
doi = {10.1109/TCAD.2017.2774822},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PelcatMDMLHNHMB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PengQ18,
author = {Xuesong Peng and
Weikang Qian},
title = {Stochastic Circuit Synthesis by Cube Assignment},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {12},
pages = {3109--3122},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2789725},
doi = {10.1109/TCAD.2018.2789725},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PengQ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PiccolboniGC18,
author = {Luca Piccolboni and
Giuseppe Di Guglielmo and
Luca P. Carloni},
title = {{PAGURUS:} Low-Overhead Dynamic Information Flow Tracking on Loosely
Coupled Accelerators},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2685--2696},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857321},
doi = {10.1109/TCAD.2018.2857321},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PiccolboniGC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PinxtenGHB18,
author = {Joost van Pinxten and
Marc Geilen and
Martijn Hendriks and
Twan Basten},
title = {Parametric Critical Path Analysis for Event Networks With Minimal
and Maximal Time Lags},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2697--2708},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857360},
doi = {10.1109/TCAD.2018.2857360},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/PinxtenGHB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz18,
author = {Irith Pomeranz},
title = {Improving the Diagnosability of Scan Chain Faults Under Transparent-Scan
by Observation Points},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {6},
pages = {1278--1287},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2748020},
doi = {10.1109/TCAD.2017.2748020},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz18a,
author = {Irith Pomeranz},
title = {An Initialization Process to Support Online Testing Based on Output
Comparison for Identical Finite-State Machines},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {7},
pages = {1494--1504},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2750060},
doi = {10.1109/TCAD.2017.2750060},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz18a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz18b,
author = {Irith Pomeranz},
title = {Autonomous Multicycle Tests With Low Storage and Test Application
Time Overheads},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {9},
pages = {1881--1892},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2774269},
doi = {10.1109/TCAD.2017.2774269},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz18b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PoulosV18,
author = {Zissis Poulos and
Andreas G. Veneris},
title = {Failure Triage in {RTL} Regression Verification},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {9},
pages = {1893--1906},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2783303},
doi = {10.1109/TCAD.2017.2783303},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PoulosV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/QianM18,
author = {Tao Qian and
Frank Mueller},
title = {A Failure Recovery Protocol for Software-Defined Real-Time Networks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2222--2232},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857299},
doi = {10.1109/TCAD.2018.2857299},
timestamp = {Mon, 22 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/QianM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/QiuLZWQ18,
author = {Pengfei Qiu and
Yongqiang Lyu and
Jiliang Zhang and
Dongsheng Wang and
Gang Qu},
title = {Control Flow Integrity Based on Lightweight Encryption Architecture},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {7},
pages = {1358--1369},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2748000},
doi = {10.1109/TCAD.2017.2748000},
timestamp = {Wed, 07 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/QiuLZWQ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RahmatiS18,
author = {Dara Rahmati and
Hamid Sarbazi{-}Azad},
title = {Classified Round Robin: {A} Simple Prioritized Arbitration to Equip
Best Effort NoCs With Effective Hard QoS},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {1},
pages = {257--269},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2693263},
doi = {10.1109/TCAD.2017.2693263},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RahmatiS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RichmondAK18,
author = {Dustin Richmond and
Alric Althoff and
Ryan Kastner},
title = {Synthesizable Higher-Order Functions for {C++}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2835--2844},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857259},
doi = {10.1109/TCAD.2018.2857259},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RichmondAK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RossiTRAB18,
author = {Daniele Rossi and
Vasileios Tenentes and
Sudhakar M. Reddy and
Bashir M. Al{-}Hashimi and
Andrew D. Brown},
title = {Exploiting Aging Benefits for the Design of Reliable Drowsy Cache
Memories},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {7},
pages = {1345--1357},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2729399},
doi = {10.1109/TCAD.2017.2729399},
timestamp = {Mon, 09 May 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RossiTRAB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SN18,
author = {Jyothi Krishna V. S and
Rupesh Nasre},
title = {Optimizing Graph Algorithms in Asymmetric Multicore Processors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2673--2684},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2858366},
doi = {10.1109/TCAD.2018.2858366},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SaadatBP18,
author = {Hassaan Saadat and
Haseeb Bokhari and
Sri Parameswaran},
title = {Minimally Biased Multipliers for Approximate Integer and Floating-Point
Multiplication},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2623--2635},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857262},
doi = {10.1109/TCAD.2018.2857262},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/SaadatBP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SahooSSMRR18,
author = {Debiprasanna Sahoo and
Swaraj Sha and
Manoranjan Satpathy and
Madhu Mutyam and
S. Ramesh and
Partha S. Roop},
title = {Formal Modeling and Verification of Controllers for a Family of {DRAM}
Caches},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2485--2496},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857318},
doi = {10.1109/TCAD.2018.2857318},
timestamp = {Mon, 03 May 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SahooSSMRR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SakibHBD18,
author = {Mohammad Nazmus Sakib and
Rakibul Hassan and
Satyendra N. Biswas and
Sunil R. Das},
title = {Memristor-Based High-Speed Memory Cell With Stable Successive Read
Operation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {5},
pages = {1037--1049},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2729464},
doi = {10.1109/TCAD.2017.2729464},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SakibHBD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SchwarzerWGWBT18,
author = {Tobias Schwarzer and
Andreas Weichslgartner and
Michael Gla{\ss} and
Stefan Wildermann and
Peter Brand and
J{\"{u}}rgen Teich},
title = {Symmetry-Eliminating Design Space Exploration for Hybrid Application
Mapping on Many-Core Architectures},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {2},
pages = {297--310},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2695894},
doi = {10.1109/TCAD.2017.2695894},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SchwarzerWGWBT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SeftonSASK18,
author = {Seaghan Sefton and
Taiman Siddiqui and
Nathaniel St. Amour and
Gordon Stewart and
Avinash Karanth Kodi},
title = {{GARUDA:} Designing Energy-Efficient Hardware Monitors From High-Level
Policies for Secure Information Flow},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2509--2518},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857041},
doi = {10.1109/TCAD.2018.2857041},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SeftonSASK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SenR18,
author = {Sanchari Sen and
Anand Raghunathan},
title = {Approximate Computing for Long Short Term Memory {(LSTM)} Neural Networks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2266--2276},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2858362},
doi = {10.1109/TCAD.2018.2858362},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SenR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SenguptaRM18,
author = {Anirban Sengupta and
Dipanjan Roy and
Saraju P. Mohanty},
title = {Triple-Phase Watermarking for Reusable {IP} Core Protection During
Architecture Synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {4},
pages = {742--755},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2729341},
doi = {10.1109/TCAD.2017.2729341},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SenguptaRM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShiPYC18,
author = {Weiwei Shi and
An Pan and
Shi Yu and
Chiu{-}sing Choy},
title = {A Subthreshold Baseband Processor Core Design With Custom Modules
and Cells for Passive {RFID} Tags},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {1},
pages = {159--167},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2764073},
doi = {10.1109/TCAD.2017.2764073},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShiPYC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShinKPPPY18,
author = {Hyunsung Shin and
Dongyoung Kim and
Eunhyeok Park and
Sungho Park and
Yongsik Park and
Sungjoo Yoo},
title = {McDRAM: Low Latency and Energy-Efficient Matrix Computations in {DRAM}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2613--2622},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857044},
doi = {10.1109/TCAD.2018.2857044},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShinKPPPY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShirazH18,
author = {Sumayya Shiraz and
Osman Hasan},
title = {A Library for Combinational Circuit Verification Using the {HOL} Theorem
Prover},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {2},
pages = {512--516},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2705049},
doi = {10.1109/TCAD.2017.2705049},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShirazH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShirinzadehSGD18,
author = {Saeideh Shirinzadeh and
Mathias Soeken and
Pierre{-}Emmanuel Gaillardon and
Rolf Drechsler},
title = {Logic Synthesis for RRAM-Based In-Memory Computing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {7},
pages = {1422--1435},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2750064},
doi = {10.1109/TCAD.2017.2750064},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShirinzadehSGD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShomalnasabZ18,
author = {Gholamreza Shomalnasab and
Lihong Zhang},
title = {Density-Uniformity-Aware Analog Layout Retargeting},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {10},
pages = {1999--2012},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2789728},
doi = {10.1109/TCAD.2018.2789728},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShomalnasabZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShonikerOCHRP18,
author = {Michael Shoniker and
Oleg Oleynikov and
Bruce F. Cockburn and
Jie Han and
Manish Rana and
Witold Pedrycz},
title = {Automatic Selection of Process Corner Simulations for Faster Design
Verification},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {6},
pages = {1312--1316},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2748027},
doi = {10.1109/TCAD.2017.2748027},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShonikerOCHRP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SoltaniyehKO18,
author = {Mohammadreza Soltaniyeh and
Ismail Kadayif and
Ozcan Ozturk},
title = {Classifying Data Blocks at Subpage Granularity With an On-Chip Page
Table to Improve Coherence in Tiled CMPs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {4},
pages = {806--819},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2729280},
doi = {10.1109/TCAD.2017.2729280},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SoltaniyehKO18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SonAY18,
author = {Mungyu Son and
Junwhan Ahn and
Sungjoo Yoo},
title = {Nonvolatile Write Buffer-Based Journaling Bypass for Storage Write
Reduction in Mobile Devices},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {9},
pages = {1747--1759},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2774192},
doi = {10.1109/TCAD.2017.2774192},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SonAY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/StratigopoulosS18,
author = {Haralampos{-}G. D. Stratigopoulos and
Christian Streitwieser},
title = {Adaptive Test With Test Escape Estimation for Mixed-Signal ICs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {10},
pages = {2125--2138},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2783302},
doi = {10.1109/TCAD.2017.2783302},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/StratigopoulosS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SubramanyanHVGM18,
author = {Pramod Subramanyan and
Bo{-}Yuan Huang and
Yakir Vizel and
Aarti Gupta and
Sharad Malik},
title = {Template-Based Parameterized Synthesis of Uniform Instruction-Level
Abstractions for SoC Verification},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {8},
pages = {1692--1705},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2764482},
doi = {10.1109/TCAD.2017.2764482},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SubramanyanHVGM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SunDSCT18,
author = {Zeyu Sun and
Ertugrul Demircan and
Mehul D. Shroff and
Chase Cook and
Sheldon X.{-}D. Tan},
title = {Fast Electromigration Immortality Analysis for Multisegment Copper
Interconnect Wires},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {12},
pages = {3137--3150},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2801221},
doi = {10.1109/TCAD.2018.2801221},
timestamp = {Fri, 19 Feb 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/SunDSCT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SunGJCGDY18,
author = {Jinghao Sun and
Nan Guan and
Xu Jiang and
Shuangshuang Chang and
Zhishan Guo and
Qingxu Deng and
Wang Yi},
title = {A Capacity Augmentation Bound for Real-Time Constrained-Deadline Parallel
Tasks Under {GEDF}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2200--2211},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857362},
doi = {10.1109/TCAD.2018.2857362},
timestamp = {Mon, 23 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/SunGJCGDY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SyafalniSW18,
author = {Infall Syafalni and
Tsutomu Sasao and
Xiaoqing Wen},
title = {A Method to Detect Bit Flips in a Soft-Error Resilient {TCAM}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {6},
pages = {1185--1196},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2748019},
doi = {10.1109/TCAD.2017.2748019},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SyafalniSW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Szczesny18,
author = {Szymon Szczesny},
title = {HDL-Based Synthesis System With Debugger for Current-Mode {FPAA}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {5},
pages = {915--926},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2740295},
doi = {10.1109/TCAD.2017.2740295},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Szczesny18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TagliaviniRMB18,
author = {Giuseppe Tagliavini and
Davide Rossi and
Andrea Marongiu and
Luca Benini},
title = {Synergistic {HW/SW} Approximation Techniques for Ultralow-Power Parallel
Computing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {5},
pages = {982--995},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2016.2633474},
doi = {10.1109/TCAD.2016.2633474},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TagliaviniRMB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TangICK18,
author = {Jack Tang and
Mohamed Ibrahim and
Krishnendu Chakrabarty and
Ramesh Karri},
title = {Secure Randomized Checkpointing for Digital Microfluidic Biochips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {6},
pages = {1119--1132},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2748030},
doi = {10.1109/TCAD.2017.2748030},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/TangICK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TangLZLFZ18,
author = {Ming Tang and
Yanbin Li and
Dongyan Zhao and
Yuguang Li and
Fei Yan and
Huanguo Zhang},
title = {Leak Point Locating in Hardware Implementations of Higher-Order Masking
Schemes},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {12},
pages = {3008--3019},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2789727},
doi = {10.1109/TCAD.2018.2789727},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TangLZLFZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TangXLZD18,
author = {Xiaofeng Tang and
Aiqiang Xu and
Ruifeng Li and
Min Zhu and
Jinling Dai},
title = {Simulation-Based Diagnostic Model for Automatic Testability Analysis
of Analog Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {7},
pages = {1483--1493},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2762647},
doi = {10.1109/TCAD.2017.2762647},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TangXLZD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TenentesRKAC18,
author = {Vasileios Tenentes and
Daniele Rossi and
S. Saqib Khursheed and
Bashir M. Al{-}Hashimi and
Krishnendu Chakrabarty},
title = {Leakage Current Analysis for Diagnosis of Bridge Defects in Power-Gating
Designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {4},
pages = {883--895},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2729462},
doi = {10.1109/TCAD.2017.2729462},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/TenentesRKAC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ThakkarP18,
author = {Ishan G. Thakkar and
Sudeep Pasricha},
title = {DyPhase: {A} Dynamic Phase Change Memory Architecture With Symmetric
Write Latency and Restorable Endurance},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {9},
pages = {1760--1773},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2762921},
doi = {10.1109/TCAD.2017.2762921},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ThakkarP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TorresWND18,
author = {Frank Sill Torres and
Robert Wille and
Philipp Niemann and
Rolf Drechsler},
title = {An Energy-Aware Model for the Logic Synthesis of Quantum-Dot Cellular
Automata},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {12},
pages = {3031--3041},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2789782},
doi = {10.1109/TCAD.2018.2789782},
timestamp = {Tue, 24 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/TorresWND18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TsengLFMLHAS18,
author = {Tsun{-}Ming Tseng and
Mengchu Li and
Daniel Nestor Freitas and
Travis McAuley and
Bing Li and
Tsung{-}Yi Ho and
Ismail Emre Araci and
Ulf Schlichtmann},
title = {Columba 2.0: {A} Co-Layout Synthesis Tool for Continuous-Flow Microfluidic
Biochips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {8},
pages = {1588--1601},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2760628},
doi = {10.1109/TCAD.2017.2760628},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TsengLFMLHAS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TsimpourlasPBS18,
author = {Foivos Tsimpourlas and
Lazaros Papadopoulos and
Anastasios Bartsokas and
Dimitrios Soudris},
title = {A Design Space Exploration Framework for Convolutional Neural Networks
Implemented on Edge Devices},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2212--2221},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857280},
doi = {10.1109/TCAD.2018.2857280},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TsimpourlasPBS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TuYHZCW18,
author = {Le Tu and
Yuelai Yuan and
Kan Huang and
Xiaoqiang Zhang and
Dihu Chen and
Zixin Wang},
title = {Improved Synthesis of Compressor Trees in High-Level Synthesis for
Modern FPGAs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {12},
pages = {3206--3210},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2801241},
doi = {10.1109/TCAD.2018.2801241},
timestamp = {Thu, 19 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TuYHZCW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ValiN18,
author = {Amin Vali and
Nicola Nicolici},
title = {Bit-Flip Detection-Driven Selection of Trace Signals},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {5},
pages = {1076--1089},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2729458},
doi = {10.1109/TCAD.2017.2729458},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ValiN18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VercruyceVS18,
author = {Dries Vercruyce and
Elias Vansteenkiste and
Dirk Stroobandt},
title = {How Preserving Circuit Design Hierarchy During {FPGA} Packing Leads
to Better Performance},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {3},
pages = {629--642},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2717786},
doi = {10.1109/TCAD.2017.2717786},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/VercruyceVS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VijayanKECT18,
author = {Arunkumar Vijayan and
Saman Kiamehr and
Mojtaba Ebrahimi and
Krishnendu Chakrabarty and
Mehdi Baradaran Tahoori},
title = {Online Soft-Error Vulnerability Estimation for Memory Arrays and Logic
Cores},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {2},
pages = {499--511},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2706558},
doi = {10.1109/TCAD.2017.2706558},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/VijayanKECT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VijayanKKCT18,
author = {Arunkumar Vijayan and
Abhishek Koneru and
Saman Kiamehr and
Krishnendu Chakrabarty and
Mehdi Baradaran Tahoori},
title = {Fine-Grained Aging-Induced Delay Prediction Based on the Monitoring
of Run-Time Stress},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {5},
pages = {1064--1075},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2016.2620903},
doi = {10.1109/TCAD.2016.2620903},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/VijayanKKCT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VijayanKOCT18,
author = {Arunkumar Vijayan and
Saman Kiamehr and
Fabian Oboril and
Krishnendu Chakrabarty and
Mehdi Baradaran Tahoori},
title = {Workload-Aware Static Aging Monitoring and Mitigation of Timing-Critical
Flip-Flops},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {10},
pages = {2098--2110},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2778254},
doi = {10.1109/TCAD.2017.2778254},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/VijayanKOCT18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WagaH18,
author = {Masaki Waga and
Ichiro Hasuo},
title = {Moore-Machine Filtering for Timed and Untimed Pattern Matching},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2649--2660},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857358},
doi = {10.1109/TCAD.2018.2857358},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WagaH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangDTHZ18,
author = {Dekui Wang and
Zhenhua Duan and
Cong Tian and
Bohu Huang and
Nan Zhang},
title = {A Runtime Optimization Approach for {FPGA} Routing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {8},
pages = {1706--1710},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2768416},
doi = {10.1109/TCAD.2017.2768416},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangDTHZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangH18,
author = {Chih{-}Hao Wang and
Tong{-}Yu Hsieh},
title = {On Probability of Detection Lossless Concurrent Error Detection Based
on Implications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {5},
pages = {1090--1103},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2740289},
doi = {10.1109/TCAD.2017.2740289},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangHCKL18,
author = {Wei{-}Chen Wang and
Chien{-}Chung Ho and
Yuan{-}Hao Chang and
Tei{-}Wei Kuo and
Ping{-}Hsien Lin},
title = {Scrubbing-Aware Secure Deletion for 3-D {NAND} Flash},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2790--2801},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857260},
doi = {10.1109/TCAD.2018.2857260},
timestamp = {Wed, 04 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangHCKL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangHZJ18,
author = {Juan Wang and
Zhi Hong and
Yuhan Zhang and
Yier Jin},
title = {Enabling Security-Enhanced Attestation With Intel {SGX} for Remote
Terminal and IoT},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {1},
pages = {88--96},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2750067},
doi = {10.1109/TCAD.2017.2750067},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangHZJ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangLHL18,
author = {Ying Wang and
Huawei Li and
Yinhe Han and
Xiaowei Li},
title = {A Low Overhead In-Network Data Compressor for the Memory Hierarchy
of Chip Multiprocessors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {6},
pages = {1265--1277},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2729404},
doi = {10.1109/TCAD.2017.2729404},
timestamp = {Tue, 23 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangLHL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangLL18,
author = {Ying Wang and
Huawei Li and
Xiaowei Li},
title = {A Case of On-Chip Memory Subsystem Design for Low-Power {CNN} Accelerators},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {10},
pages = {1971--1984},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2778060},
doi = {10.1109/TCAD.2017.2778060},
timestamp = {Thu, 11 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangLL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangLLZ18,
author = {Xiaoping Wang and
Shuai Li and
Hui Liu and
Zhigang Zeng},
title = {A Compact Scheme of Reading and Writing for Memristor-Based Multivalued
Memory},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {7},
pages = {1505--1509},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2753199},
doi = {10.1109/TCAD.2017.2753199},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangLLZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangLYYCZZ18,
author = {Mengshuo Wang and
Wenlong Lv and
Fan Yang and
Changhao Yan and
Wei Cai and
Dian Zhou and
Xuan Zeng},
title = {Efficient Yield Optimization for Analog and {SRAM} Circuits via Gaussian
Process Regression and Adaptive Yield Estimation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {10},
pages = {1929--1942},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2778061},
doi = {10.1109/TCAD.2017.2778061},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangLYYCZZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangWCZ18,
author = {Xiaoping Wang and
Qian Wu and
Qiao Chen and
Zhigang Zeng},
title = {A Novel Design for Memristor-Based Multiplexer Via NOT-Material Implication},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {7},
pages = {1436--1444},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2753204},
doi = {10.1109/TCAD.2017.2753204},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangWCZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangWLZX18,
author = {Shunzhuo Wang and
Fei Wu and
Zhonghai Lu and
Jiaona Zhou and
Changsheng Xie},
title = {{WARD:} Wear Aware {RAID} Design Within SSDs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2918--2928},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2858339},
doi = {10.1109/TCAD.2018.2858339},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangWLZX18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangZA18,
author = {Lingtai Wang and
Naijun Zhan and
Jie An},
title = {The Opacity of Real-Time Automata},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2845--2856},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857363},
doi = {10.1109/TCAD.2018.2857363},
timestamp = {Tue, 25 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangZA18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangZG18,
author = {Wei{-}Che Wang and
Charles Zhao and
Puneet Gupta},
title = {Assessing Layout Density Benefits of Vertical Channel Devices},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {12},
pages = {3211--3215},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2782758},
doi = {10.1109/TCAD.2017.2782758},
timestamp = {Thu, 28 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangZG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangZHST18,
author = {Xiaoxiao Wang and
Dongrong Zhang and
Miao Tony He and
Donglin Su and
Mark M. Tehranipoor},
title = {Secure Scan and Test Using Obfuscation Throughout Supply Chain},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {9},
pages = {1867--1880},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2772817},
doi = {10.1109/TCAD.2017.2772817},
timestamp = {Mon, 26 Sep 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangZHST18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangZYHWC18,
author = {Qin Wang and
Hao Zou and
Hailong Yao and
Tsung{-}Yi Ho and
Robert Wille and
Yici Cai},
title = {Physical Co-Design of Flow and Control Layers for Flow-Based Microfluidic
Biochips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {6},
pages = {1157--1170},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2748003},
doi = {10.1109/TCAD.2017.2748003},
timestamp = {Tue, 17 Aug 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangZYHWC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WeiZCCCZHY18,
author = {Tongquan Wei and
Junlong Zhou and
Kun Cao and
Peijin Cong and
Mingsong Chen and
Gongxuan Zhang and
Xiaobo Sharon Hu and
Jianming Yan},
title = {Cost-Constrained QoS Optimization for Approximate Computation Real-Time
Tasks in Heterogeneous MPSoCs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {9},
pages = {1733--1746},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2772896},
doi = {10.1109/TCAD.2017.2772896},
timestamp = {Thu, 17 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/WeiZCCCZHY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WessDJ18,
author = {Matthias Wess and
Sai Manoj Pudukotai Dinakarrao and
Axel Jantsch},
title = {Weighted Quantization-Regularization in DNNs for Weight Memory Minimization
Toward {HW} Implementation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2929--2939},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857080},
doi = {10.1109/TCAD.2018.2857080},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WessDJ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WuYCK18,
author = {Chun{-}Feng Wu and
Ming{-}Chang Yang and
Yuan{-}Hao Chang and
Tei{-}Wei Kuo},
title = {Hot-Spot Suppression for Resource-Constrained Image Recognition Devices
With Nonvolatile Memory},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2567--2577},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2858459},
doi = {10.1109/TCAD.2018.2858459},
timestamp = {Tue, 05 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/WuYCK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XiaLTGCYCWXY18,
author = {Lixue Xia and
Boxun Li and
Tianqi Tang and
Peng Gu and
Pai{-}Yu Chen and
Shimeng Yu and
Yu Cao and
Yu Wang and
Yuan Xie and
Huazhong Yang},
title = {{MNSIM:} Simulation Platform for Memristor-Based Neuromorphic Computing
System},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {5},
pages = {1009--1022},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2729466},
doi = {10.1109/TCAD.2017.2729466},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/XiaLTGCYCWXY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XieNTHB18,
author = {Lei Xie and
Hoang Anh Du Nguyen and
Mottaqiallah Taouil and
Said Hamdioui and
Koen Bertels},
title = {A Mapping Methodology of Boolean Logic Circuits on Memristor Crossbar},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {2},
pages = {311--323},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2695880},
doi = {10.1109/TCAD.2017.2695880},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/XieNTHB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XuLLMNKKP18,
author = {Xiaoqing Xu and
Yibo Lin and
Meng Li and
Tetsuaki Matsunawa and
Shigeki Nojima and
Chikaaki Kodama and
Toshiya Kotani and
David Z. Pan},
title = {Subresolution Assist Feature Generation With Supervised Data Learning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {6},
pages = {1225--1236},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2748029},
doi = {10.1109/TCAD.2017.2748029},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/XuLLMNKKP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XuLWYLXSH18,
author = {Xiaowei Xu and
Feng Lin and
Aosen Wang and
Xinwei Yao and
Qing Lu and
Wenyao Xu and
Yiyu Shi and
Yu Hu},
title = {Accelerating Dynamic Time Warping With Memristor-Based Customized
Fabrics},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {4},
pages = {729--741},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2729344},
doi = {10.1109/TCAD.2017.2729344},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/XuLWYLXSH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XueLB18,
author = {Yang Xue and
Xin Li and
Ronald D. Blanton},
title = {Improving Diagnostic Resolution of Failing ICs Through Learning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {6},
pages = {1288--1297},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2016.2611499},
doi = {10.1109/TCAD.2016.2611499},
timestamp = {Thu, 18 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/XueLB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Yan18,
author = {Jin{-}Tai Yan},
title = {On-Chip Optical Channel Routing for Signal Loss Minimization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {8},
pages = {1654--1666},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2760508},
doi = {10.1109/TCAD.2017.2760508},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Yan18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YanYTLW18,
author = {Jiale Yan and
Shouyi Yin and
Fengbin Tu and
Leibo Liu and
Shaojun Wei},
title = {{GNA:} Reconfigurable and Efficient Architecture for Generative Network
Acceleration},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2519--2529},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857258},
doi = {10.1109/TCAD.2018.2857258},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YanYTLW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YangDCG18,
author = {Yoon Seok Yang and
Hrishikesh Deshpande and
Gwan Choi and
Paul V. Gratz},
title = {{SDPR:} Improving Latency and Bandwidth in On-Chip Interconnect Through
Simultaneous Dual-Path Routing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {3},
pages = {545--558},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2016.2570428},
doi = {10.1109/TCAD.2016.2570428},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/YangDCG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YangWHTC18,
author = {Shaofu Yang and
Zhi{-}Yuan Wen and
Shi{-}Yu Huang and
Kun{-}Han Tsai and
Wu{-}Tung Cheng},
title = {Circuit and Methodology for Testing Small Delay Faults in the Clock
Network},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {10},
pages = {2087--2097},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2789779},
doi = {10.1109/TCAD.2018.2789779},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YangWHTC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YangYHXC18,
author = {Kailin Yang and
Hailong Yao and
Tsung{-}Yi Ho and
Kunze Xin and
Yici Cai},
title = {{AARF:} Any-Angle Routing for Flow-Based Microfluidic Biochips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {12},
pages = {3042--3055},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2789356},
doi = {10.1109/TCAD.2018.2789356},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YangYHXC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YangZBYZSZ18,
author = {Yishi Yang and
Hengliang Zhu and
Zhaori Bi and
Changhao Yan and
Dian Zhou and
Yangfeng Su and
Xuan Zeng},
title = {Smart-MSP: {A} Self-Adaptive Multiple Starting Point Optimization
Approach for Analog Circuit Synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {3},
pages = {531--544},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2729461},
doi = {10.1109/TCAD.2017.2729461},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YangZBYZSZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YeGHL18,
author = {Jing Ye and
Qingli Guo and
Yu Hu and
Xiaowei Li},
title = {Deterministic and Probabilistic Diagnostic Challenge Generation for
Arbiter Physical Unclonable Function},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {12},
pages = {3186--3197},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2801224},
doi = {10.1109/TCAD.2018.2801224},
timestamp = {Mon, 22 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YeGHL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YenCC18,
author = {Miao{-}Chiang Yen and
Shih{-}Yi Chang and
Li{-}Pin Chang},
title = {Lightweight, Integrated Data Deduplication for Write Stress Reduction
of Mobile Flash Storage},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2590--2600},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857322},
doi = {10.1109/TCAD.2018.2857322},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YenCC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YinXMOLW18,
author = {Shouyi Yin and
Zhicong Xie and
Chenyue Meng and
Peng Ouyang and
Leibo Liu and
Shaojun Wei},
title = {Memory Partitioning for Parallel Multipattern Data Access in Multiple
Data Arrays},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {2},
pages = {431--444},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2693274},
doi = {10.1109/TCAD.2017.2693274},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YinXMOLW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YoonR18,
author = {Insik Yoon and
Arijit Raychowdhury},
title = {Modeling and Analysis of Magnetic Field Induced Coupling on Embedded
{STT-MRAM} Arrays},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {2},
pages = {337--349},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2697963},
doi = {10.1109/TCAD.2017.2697963},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YoonR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YuCM18,
author = {Cunxi Yu and
Maciej J. Ciesielski and
Alan Mishchenko},
title = {Fast Algebraic Rewriting Based on And-Inverter Graphs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {9},
pages = {1907--1911},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2772854},
doi = {10.1109/TCAD.2017.2772854},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YuCM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YuFCSC18,
author = {Tao{-}Chun Yu and
Shao{-}Yun Fang and
Chia{-}Ching Chen and
Yulong Sun and
Poki Chen},
title = {Device Array Layout Synthesis With Nonlinear Gradient Compensation
for a High-Accuracy Current-Steering {DAC}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {4},
pages = {717--728},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2729402},
doi = {10.1109/TCAD.2017.2729402},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YuFCSC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YuWEX18,
author = {Zhibin Yu and
Jing Wang and
Lieven Eeckhout and
Chengzhong Xu},
title = {{QIG:} Quantifying the Importance and Interaction of {GPGPU} Architecture
Parameters},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {6},
pages = {1211--1224},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2698026},
doi = {10.1109/TCAD.2017.2698026},
timestamp = {Tue, 11 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YuWEX18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YuXLZ18,
author = {Wenjian Yu and
Zhezhao Xu and
Bo Li and
Cheng Zhuo},
title = {Floating Random Walk-Based Capacitance Simulation Considering General
Floating Metals},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {8},
pages = {1711--1715},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2782770},
doi = {10.1109/TCAD.2017.2782770},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YuXLZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhaiNS18,
author = {Jiali Teddy Zhai and
Sobhan Niknam and
Todor P. Stefanov},
title = {Modeling, Analysis, and Hard Real-Time Scheduling of Adaptive Streaming
Applications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2636--2648},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2858365},
doi = {10.1109/TCAD.2018.2858365},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhaiNS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhakatayevKCL18,
author = {Aidyn Zhakatayev and
Kyounghoon Kim and
Kiyoung Choi and
Jongeun Lee},
title = {An Efficient and Accurate Stochastic Number Generator Using Even-Distribution
Coding},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {12},
pages = {3056--3066},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2789732},
doi = {10.1109/TCAD.2018.2789732},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhakatayevKCL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhangESAH18,
author = {Zhenya Zhang and
Gidon Ernst and
Sean Sedwards and
Paolo Arcaini and
Ichiro Hasuo},
title = {Two-Layered Falsification of Hybrid Systems Guided by Monte Carlo
Tree Search},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2894--2905},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2858463},
doi = {10.1109/TCAD.2018.2858463},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhangESAH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhangGJL18,
author = {Wei Zhang and
Nan Guan and
Lei Ju and
Weichen Liu},
title = {Analyzing Data Cache Related Preemption Delay With Multiple Preemptions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2255--2265},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857079},
doi = {10.1109/TCAD.2018.2857079},
timestamp = {Tue, 07 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ZhangGJL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhangLLSS18,
author = {Grace Li Zhang and
Bing Li and
Jinglan Liu and
Yiyu Shi and
Ulf Schlichtmann},
title = {Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative
Learning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {2},
pages = {392--405},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2702632},
doi = {10.1109/TCAD.2017.2702632},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ZhangLLSS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhangYLZCL18,
author = {Yifan Zhang and
Zhengfeng Yang and
Wang Lin and
Huibiao Zhu and
Xin Chen and
Xuandong Li},
title = {Safety Verification of Nonlinear Hybrid Systems Based on Bilinear
Programming},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2768--2778},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2858383},
doi = {10.1109/TCAD.2018.2858383},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhangYLZCL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhaoBG18,
author = {Zhuoran Zhao and
Kamyar Mirzazad Barijough and
Andreas Gerstlauer},
title = {DeepThings: Distributed Adaptive Deep Learning Inference on Resource-Constrained
IoT Edge Clusters},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2348--2359},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2858384},
doi = {10.1109/TCAD.2018.2858384},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhaoBG18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhaoGZ18,
author = {Yecheng Zhao and
Vinit Gala and
Haibo Zeng},
title = {A Unified Framework for Period and Priority Optimization in Distributed
Hard Real-Time Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {11},
pages = {2188--2199},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2857380},
doi = {10.1109/TCAD.2018.2857380},
timestamp = {Thu, 13 Apr 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhaoGZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhouNS18,
author = {Yuhan Zhou and
Robert D. Nevels and
Weiping Shi},
title = {Capacitance Extraction With Provably Good Absorbing Boundary Conditions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {10},
pages = {2013--2021},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2018.2789781},
doi = {10.1109/TCAD.2018.2789781},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhouNS18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhuHZPZZ18,
author = {Hengliang Zhu and
Feng Hu and
Hao Zhou and
David Z. Pan and
Dian Zhou and
Xuan Zeng},
title = {Interlayer Cooling Network Design for High-Performance 3D ICs Using
Channel Patterning and Pruning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {4},
pages = {770--781},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2731683},
doi = {10.1109/TCAD.2017.2731683},
timestamp = {Tue, 16 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhuHZPZZ18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZouCSW18,
author = {Minhui Zou and
Xiaotong Cui and
Liang Shi and
Kaijie Wu},
title = {Potential Trigger Detection for Hardware Trojans},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {7},
pages = {1384--1395},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2753201},
doi = {10.1109/TCAD.2017.2753201},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZouCSW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZulehnerW18,
author = {Alwin Zulehner and
Robert Wille},
title = {One-Pass Design of Reversible Circuits: Combining Embedding and Synthesis
for Reversible Logic},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {37},
number = {5},
pages = {996--1008},
year = {2018},
url = {https://doi.org/10.1109/TCAD.2017.2729468},
doi = {10.1109/TCAD.2017.2729468},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZulehnerW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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