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@article{DBLP:journals/thipeac/BosschereLMNOPRSSST07,
  author       = {Koen De Bosschere and
                  Wayne Luk and
                  Xavier Martorell and
                  Nacho Navarro and
                  Michael F. P. O'Boyle and
                  Dionisios N. Pnevmatikatos and
                  Alex Ram{\'{\i}}rez and
                  Pascal Sainrat and
                  Andr{\'{e}} Seznec and
                  Per Stenstr{\"{o}}m and
                  Olivier Temam},
  title        = {High-Performance Embedded Architecture and Compilation Roadmap},
  journal      = {Trans. High Perform. Embed. Archit. Compil.},
  volume       = {1},
  pages        = {5--29},
  year         = {2007},
  url          = {https://doi.org/10.1007/978-3-540-71528-3\_2},
  doi          = {10.1007/978-3-540-71528-3\_2},
  timestamp    = {Mon, 18 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/thipeac/BosschereLMNOPRSSST07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/thipeac/BuytaertVEB07,
  author       = {Dries Buytaert and
                  Kris Venstermans and
                  Lieven Eeckhout and
                  Koen De Bosschere},
  title        = {{GCH:} Hints for Triggering Garbage Collections},
  journal      = {Trans. High Perform. Embed. Archit. Compil.},
  volume       = {1},
  pages        = {74--94},
  year         = {2007},
  url          = {https://doi.org/10.1007/978-3-540-71528-3\_6},
  doi          = {10.1007/978-3-540-71528-3\_6},
  timestamp    = {Mon, 18 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/thipeac/BuytaertVEB07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/thipeac/ChenK07,
  author       = {Guilin Chen and
                  Mahmut T. Kandemir},
  title        = {An Approach for Enhancing Inter-processor Data Locality on Chip Multiprocessors},
  journal      = {Trans. High Perform. Embed. Archit. Compil.},
  volume       = {1},
  pages        = {214--233},
  year         = {2007},
  url          = {https://doi.org/10.1007/978-3-540-71528-3\_14},
  doi          = {10.1007/978-3-540-71528-3\_14},
  timestamp    = {Mon, 18 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/thipeac/ChenK07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/thipeac/DevosBCCDS07,
  author       = {Harald Devos and
                  Kristof Beyls and
                  Mark Christiaens and
                  Jan M. Van Campenhout and
                  Erik H. D'Hollander and
                  Dirk Stroobandt},
  title        = {Finding and Applying Loop Transformations for Generating Optimized
                  {FPGA} Implementations},
  journal      = {Trans. High Perform. Embed. Archit. Compil.},
  volume       = {1},
  pages        = {159--178},
  year         = {2007},
  url          = {https://doi.org/10.1007/978-3-540-71528-3\_11},
  doi          = {10.1007/978-3-540-71528-3\_11},
  timestamp    = {Mon, 18 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/thipeac/DevosBCCDS07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/thipeac/FakhreddineAAJ07,
  author       = {Fakhreddine Ghaffari and
                  Michel Auguin and
                  Mohamed Abid and
                  Maher Ben Jemaa},
  title        = {Dynamic and On-Line Design Space Exploration for Reconfigurable Architectures},
  journal      = {Trans. High Perform. Embed. Archit. Compil.},
  volume       = {1},
  pages        = {179--193},
  year         = {2007},
  url          = {https://doi.org/10.1007/978-3-540-71528-3\_12},
  doi          = {10.1007/978-3-540-71528-3\_12},
  timestamp    = {Wed, 28 Apr 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/thipeac/FakhreddineAAJ07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/thipeac/FursinCOT07,
  author       = {Grigori Fursin and
                  Albert Cohen and
                  Michael F. P. O'Boyle and
                  Olivier Temam},
  title        = {Quick and Practical Run-Time Evaluation of Multiple Program Optimizations},
  journal      = {Trans. High Perform. Embed. Archit. Compil.},
  volume       = {1},
  pages        = {34--53},
  year         = {2007},
  url          = {https://doi.org/10.1007/978-3-540-71528-3\_4},
  doi          = {10.1007/978-3-540-71528-3\_4},
  timestamp    = {Mon, 18 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/thipeac/FursinCOT07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/thipeac/GeigerMT07,
  author       = {Michael J. Geiger and
                  Sally A. McKee and
                  Gary S. Tyson},
  title        = {Specializing Cache Structures for High Performance and Energy Conservation
                  in Embedded Systems},
  journal      = {Trans. High Perform. Embed. Archit. Compil.},
  volume       = {1},
  pages        = {54--73},
  year         = {2007},
  url          = {https://doi.org/10.1007/978-3-540-71528-3\_5},
  doi          = {10.1007/978-3-540-71528-3\_5},
  timestamp    = {Mon, 18 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/thipeac/GeigerMT07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/thipeac/KhatibBPBJBKHNJ07,
  author       = {Iyad Al Khatib and
                  Davide Bertozzi and
                  Francesco Poletti and
                  Luca Benini and
                  Axel Jantsch and
                  Mohamed Bechara and
                  Hasan Khalifeh and
                  Mazen Hajjar and
                  Rustam Nabiev and
                  Sven Jonsson},
  title        = {Hardware/Software Architecture for Real-Time {ECG} Monitoring and
                  Analysis Leveraging MPSoC Technology},
  journal      = {Trans. High Perform. Embed. Archit. Compil.},
  volume       = {1},
  pages        = {239--258},
  year         = {2007},
  url          = {https://doi.org/10.1007/978-3-540-71528-3\_16},
  doi          = {10.1007/978-3-540-71528-3\_16},
  timestamp    = {Mon, 18 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/thipeac/KhatibBPBJBKHNJ07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/thipeac/McKee07,
  author       = {Sally A. McKee},
  title        = {Introduction to Part 3},
  journal      = {Trans. High Perform. Embed. Archit. Compil.},
  volume       = {1},
  pages        = {237--238},
  year         = {2007},
  url          = {https://doi.org/10.1007/978-3-540-71528-3\_15},
  doi          = {10.1007/978-3-540-71528-3\_15},
  timestamp    = {Mon, 18 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/thipeac/McKee07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/thipeac/MolnosCHE07,
  author       = {Anca Mariana Molnos and
                  Sorin Dan Cotofana and
                  Marc J. M. Heijligers and
                  Jos T. J. van Eijndhoven},
  title        = {Static Cache Partitioning Robustness Analysis for Embedded On-Chip
                  Multi-processors},
  journal      = {Trans. High Perform. Embed. Archit. Compil.},
  volume       = {1},
  pages        = {279--297},
  year         = {2007},
  url          = {https://doi.org/10.1007/978-3-540-71528-3\_18},
  doi          = {10.1007/978-3-540-71528-3\_18},
  timestamp    = {Mon, 15 Jun 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/thipeac/MolnosCHE07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/thipeac/NethercoteBM07,
  author       = {Nicholas Nethercote and
                  Doug Burger and
                  Kathryn S. McKinley},
  title        = {Convergent Compilation Applied to Loop Unrolling},
  journal      = {Trans. High Perform. Embed. Archit. Compil.},
  volume       = {1},
  pages        = {140--158},
  year         = {2007},
  url          = {https://doi.org/10.1007/978-3-540-71528-3\_10},
  doi          = {10.1007/978-3-540-71528-3\_10},
  timestamp    = {Mon, 18 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/thipeac/NethercoteBM07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/thipeac/NingK07,
  author       = {Ke Ning and
                  David R. Kaeli},
  title        = {Power Aware External Bus Arbitration for System-on-a-Chip Embedded
                  Systems},
  journal      = {Trans. High Perform. Embed. Archit. Compil.},
  volume       = {1},
  pages        = {116--135},
  year         = {2007},
  url          = {https://doi.org/10.1007/978-3-540-71528-3\_8},
  doi          = {10.1007/978-3-540-71528-3\_8},
  timestamp    = {Mon, 18 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/thipeac/NingK07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/thipeac/OBoyleBC07,
  author       = {Michael F. P. O'Boyle and
                  Fran{\c{c}}ois Bodin and
                  Marcelo Cintra},
  title        = {Introduction to Part 2},
  journal      = {Trans. High Perform. Embed. Archit. Compil.},
  volume       = {1},
  pages        = {139},
  year         = {2007},
  url          = {https://doi.org/10.1007/978-3-540-71528-3\_9},
  doi          = {10.1007/978-3-540-71528-3\_9},
  timestamp    = {Mon, 18 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/thipeac/OBoyleBC07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/thipeac/OliverFCA07,
  author       = {John Y. Oliver and
                  Diana Franklin and
                  Frederic T. Chong and
                  Venkatesh Akella},
  title        = {Using Application Bisection Bandwidth to Guide Tile Size Selection
                  for the Synchroscalar Tile-Based Architecture},
  journal      = {Trans. High Perform. Embed. Archit. Compil.},
  volume       = {1},
  pages        = {259--278},
  year         = {2007},
  url          = {https://doi.org/10.1007/978-3-540-71528-3\_17},
  doi          = {10.1007/978-3-540-71528-3\_17},
  timestamp    = {Sat, 25 Feb 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/thipeac/OliverFCA07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/thipeac/PinterW07,
  author       = {Shlomit S. Pinter and
                  Israel Waldman},
  title        = {Selective Code Compression Scheme for Embedded Systems},
  journal      = {Trans. High Perform. Embed. Archit. Compil.},
  volume       = {1},
  pages        = {298--316},
  year         = {2007},
  url          = {https://doi.org/10.1007/978-3-540-71528-3\_19},
  doi          = {10.1007/978-3-540-71528-3\_19},
  timestamp    = {Mon, 18 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/thipeac/PinterW07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/thipeac/RyooURKFH07,
  author       = {Shane Ryoo and
                  Sain{-}Zee Ueng and
                  Christopher I. Rodrigues and
                  Robert E. Kidd and
                  Matthew I. Frank and
                  Wen{-}mei W. Hwu},
  title        = {Automatic Discovery of Coarse-Grained Parallelism in Media Applications},
  journal      = {Trans. High Perform. Embed. Archit. Compil.},
  volume       = {1},
  pages        = {194--213},
  year         = {2007},
  url          = {https://doi.org/10.1007/978-3-540-71528-3\_13},
  doi          = {10.1007/978-3-540-71528-3\_13},
  timestamp    = {Mon, 18 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/thipeac/RyooURKFH07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/thipeac/ShiLL07,
  author       = {Weidong Shi and
                  Chenghuai Lu and
                  Hsien{-}Hsin S. Lee},
  title        = {Memory-Centric Security Architecture},
  journal      = {Trans. High Perform. Embed. Archit. Compil.},
  volume       = {1},
  pages        = {95--115},
  year         = {2007},
  url          = {https://doi.org/10.1007/978-3-540-71528-3\_7},
  doi          = {10.1007/978-3-540-71528-3\_7},
  timestamp    = {Mon, 18 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/thipeac/ShiLL07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/thipeac/SonK07,
  author       = {Seung Woo Son and
                  Mahmut T. Kandemir},
  title        = {A Prefetching Algorithm for Multi-speed Disks},
  journal      = {Trans. High Perform. Embed. Archit. Compil.},
  volume       = {1},
  pages        = {317--340},
  year         = {2007},
  url          = {https://doi.org/10.1007/978-3-540-71528-3\_20},
  doi          = {10.1007/978-3-540-71528-3\_20},
  timestamp    = {Mon, 18 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/thipeac/SonK07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/thipeac/Stenstrom07,
  author       = {Per Stenstr{\"{o}}m},
  title        = {Introduction to Part 1},
  journal      = {Trans. High Perform. Embed. Archit. Compil.},
  volume       = {1},
  pages        = {33},
  year         = {2007},
  url          = {https://doi.org/10.1007/978-3-540-71528-3\_3},
  doi          = {10.1007/978-3-540-71528-3\_3},
  timestamp    = {Mon, 18 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/thipeac/Stenstrom07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/thipeac/SusuMAAM07,
  author       = {Alex E. Susu and
                  Michele Magno and
                  Andrea Acquaviva and
                  David Atienza and
                  Giovanni De Micheli},
  title        = {Reconfiguration Strategies for Environmentally Powered Devices: Theoretical
                  Analysis and Experimental Validation},
  journal      = {Trans. High Perform. Embed. Archit. Compil.},
  volume       = {1},
  pages        = {341--360},
  year         = {2007},
  url          = {https://doi.org/10.1007/978-3-540-71528-3\_21},
  doi          = {10.1007/978-3-540-71528-3\_21},
  timestamp    = {Sun, 25 Jul 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/thipeac/SusuMAAM07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/thipeac/Wilkes07,
  author       = {Maurice V. Wilkes},
  title        = {High Performance Processor Chips},
  journal      = {Trans. High Perform. Embed. Archit. Compil.},
  volume       = {1},
  pages        = {1--4},
  year         = {2007},
  url          = {https://doi.org/10.1007/978-3-540-71528-3\_1},
  doi          = {10.1007/978-3-540-71528-3\_1},
  timestamp    = {Mon, 18 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/thipeac/Wilkes07.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@proceedings{DBLP:journals/thipeac/2007-1,
  editor       = {Per Stenstr{\"{o}}m and
                  Michael F. P. O'Boyle and
                  Fran{\c{c}}ois Bodin and
                  Marcelo Cintra and
                  Sally A. McKee},
  title        = {Transactions on High-Performance Embedded Architectures and Compilers
                  {I}},
  series       = {Lecture Notes in Computer Science},
  volume       = {4050},
  publisher    = {Springer},
  year         = {2007},
  url          = {https://doi.org/10.1007/978-3-540-71528-3},
  doi          = {10.1007/978-3-540-71528-3},
  isbn         = {978-3-540-71527-6},
  timestamp    = {Tue, 14 May 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/thipeac/2007-1.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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