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@article{DBLP:journals/todaes/AraujoM98,
author = {Guido Araujo and
Sharad Malik},
title = {Code generation for fixed-point DSPs},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {3},
number = {2},
pages = {136--161},
year = {1998},
url = {https://doi.org/10.1145/290833.290837},
doi = {10.1145/290833.290837},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/AraujoM98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/BensoPRR98,
author = {Alfredo Benso and
Paolo Prinetto and
Maurizio Rebaudengo and
Matteo Sonza Reorda},
title = {{EXFI:} a low-cost fault injection system for embedded microprocessor-based
boards},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {3},
number = {4},
pages = {626--634},
year = {1998},
url = {https://doi.org/10.1145/296333.296351},
doi = {10.1145/296333.296351},
timestamp = {Sun, 02 Jun 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/BensoPRR98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/BhattacharyaDB98,
author = {Subhrajit Bhattacharya and
Sujit Dey and
Franc Brglez},
title = {Effects of resource sharing on circuit delay: an assignment algorithm
for clock period optimization},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {3},
number = {2},
pages = {285--307},
year = {1998},
url = {https://doi.org/10.1145/290833.290852},
doi = {10.1145/290833.290852},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/BhattacharyaDB98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/CabodiCQ98,
author = {Gianpiero Cabodi and
Paolo Camurati and
Stefano Quer},
title = {Auxiliary variables for BDD-based representation and manipulation
of Boolean functions},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {3},
number = {3},
pages = {309--340},
year = {1998},
url = {https://doi.org/10.1145/293625.293626},
doi = {10.1145/293625.293626},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/CabodiCQ98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/CampenhoutAHMB98,
author = {David Van Campenhout and
Hussain Al{-}Asaad and
John P. Hayes and
Trevor N. Mudge and
Richard B. Brown},
title = {High-level design verification of microprocessors via error modeling},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {3},
number = {4},
pages = {581--599},
year = {1998},
url = {https://doi.org/10.1145/296333.296347},
doi = {10.1145/296333.296347},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/CampenhoutAHMB98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/ChenML98,
author = {Xiao{-}Tao Chen and
Fred J. Meyer and
Fabrizio Lombardi},
title = {Structural diagnosis of interconnects by coloring},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {3},
number = {2},
pages = {249--271},
year = {1998},
url = {https://doi.org/10.1145/290833.290848},
doi = {10.1145/290833.290848},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/ChenML98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/CongKKT98,
author = {Jason Cong and
Andrew B. Kahng and
Cheng{-}Kok Koh and
Chung{-}Wen Albert Tsao},
title = {Bounded-skew clock and Steiner routing},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {3},
number = {3},
pages = {341--388},
year = {1998},
url = {https://doi.org/10.1145/293625.293628},
doi = {10.1145/293625.293628},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/CongKKT98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/DasdanRG98,
author = {Ali Dasdan and
Dinesh Ramanathan and
Rajesh K. Gupta},
title = {A timing-driven design and validation methodology for embedded real-time
systems},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {3},
number = {4},
pages = {533--553},
year = {1998},
url = {https://doi.org/10.1145/296333.296338},
doi = {10.1145/296333.296338},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/DasdanRG98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/HasteerMB98,
author = {Gagan Hasteer and
Anmol Mathur and
Prithviraj Banerjee},
title = {Efficient equivalence checking of multi-phase designs using phase
abstraction and retiming},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {3},
number = {4},
pages = {600--625},
year = {1998},
url = {https://doi.org/10.1145/296333.296348},
doi = {10.1145/296333.296348},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/HasteerMB98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/HsiungCLC98,
author = {Pao{-}Ann Hsiung and
Chung{-}Hwang Chen and
Trong{-}Yen Lee and
Sao{-}Jie Chen},
title = {{ICOS:} an intelligent concurrent object-oriented synthesis methodology
for multiprocessor systems},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {3},
number = {2},
pages = {109--135},
year = {1998},
url = {https://doi.org/10.1145/290833.290834},
doi = {10.1145/290833.290834},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/HsiungCLC98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/HugginsC98,
author = {James K. Huggins and
David Van Campenhout},
title = {Specification and verification of pipelining in the {ARM2} {RISC}
microprocessor},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {3},
number = {4},
pages = {563--580},
year = {1998},
url = {https://doi.org/10.1145/296333.296345},
doi = {10.1145/296333.296345},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/HugginsC98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/JohnsonB98,
author = {Eric W. Johnson and
Jay B. Brockman},
title = {Measurement and analysis of sequential design processes},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {3},
number = {1},
pages = {1--20},
year = {1998},
url = {https://doi.org/10.1145/270580.270581},
doi = {10.1145/270580.270581},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/JohnsonB98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/JoneT98,
author = {Wen{-}Ben Jone and
K. S. Tsai},
title = {Confidence analysis for defect-level estimation of {VLSI} random testing},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {3},
number = {3},
pages = {389--407},
year = {1998},
url = {https://doi.org/10.1145/293625.293629},
doi = {10.1145/293625.293629},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/JoneT98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/KhordocC98,
author = {Karim Khordoc and
Eduard Cerny},
title = {Semantics and verification of action diagrams with linear timing},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {3},
number = {1},
pages = {21--50},
year = {1998},
url = {https://doi.org/10.1145/270580.270582},
doi = {10.1145/270580.270582},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/KhordocC98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/KochRK98,
author = {Gernot Koch and
Wolfgang Rosenstiel and
Udo Kebschull},
title = {Breakpoints and breakpoint detection in source-level emulation},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {3},
number = {2},
pages = {209--230},
year = {1998},
url = {https://doi.org/10.1145/290833.290843},
doi = {10.1145/290833.290843},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/KochRK98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/LiaoKTD98,
author = {Stan Y. Liao and
Kurt Keutzer and
Steven W. K. Tjiang and
Srinivas Devadas},
title = {A new viewpoint on code generation for directed acyclic graphs},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {3},
number = {1},
pages = {51--75},
year = {1998},
url = {https://doi.org/10.1145/270580.270583},
doi = {10.1145/270580.270583},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/LiaoKTD98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/MathurDG98,
author = {Anmol Mathur and
Ali Dasdan and
Rajesh K. Gupta},
title = {Rate analysis for embedded systems},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {3},
number = {3},
pages = {408--436},
year = {1998},
url = {https://doi.org/10.1145/293625.293631},
doi = {10.1145/293625.293631},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/MathurDG98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/Mehta98,
author = {Dinesh P. Mehta},
title = {Estimating the storage requirements of the rectangular and L-shaped
corner stitching data structures},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {3},
number = {2},
pages = {272--284},
year = {1998},
url = {https://doi.org/10.1145/290833.290850},
doi = {10.1145/290833.290850},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/Mehta98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/PanL98,
author = {Peichen Pan and
C. L. Liu},
title = {Optimal clock period {FPGA} technology mapping for sequential circuits},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {3},
number = {3},
pages = {437--462},
year = {1998},
url = {https://doi.org/10.1145/293625.293632},
doi = {10.1145/293625.293632},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/PanL98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/PasseroneSLMMPS98,
author = {Claudio Passerone and
Claudio Sanso{\`{e}} and
Luciano Lavagno and
Patrick C. McGeer and
Jonathan Martin and
Roberto Passerone and
Alberto L. Sangiovanni{-}Vincentelli},
title = {Modeling reactive systems in Java},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {3},
number = {4},
pages = {515--523},
year = {1998},
url = {https://doi.org/10.1145/296333.296334},
doi = {10.1145/296333.296334},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/PasseroneSLMMPS98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/PomeranzR98,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Functional test generation for delay faults in combinational circuits},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {3},
number = {2},
pages = {231--248},
year = {1998},
url = {https://doi.org/10.1145/290833.290845},
doi = {10.1145/290833.290845},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/PomeranzR98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/RajanFYL98,
author = {Sreeranga P. Rajan and
Masahiro Fujita and
K. Yuan and
Mike Tien{-}Chien Lee},
title = {{ATM} switch design by high-level modeling, formal verification and
high-level synthesis},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {3},
number = {4},
pages = {554--562},
year = {1998},
url = {https://doi.org/10.1145/296333.296342},
doi = {10.1145/296333.296342},
timestamp = {Tue, 10 Nov 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/RajanFYL98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/RiepeS98,
author = {Michael A. Riepe and
Karem A. Sakallah},
title = {The edge-based design rule model revisited},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {3},
number = {3},
pages = {463--486},
year = {1998},
url = {https://doi.org/10.1145/293625.293633},
doi = {10.1145/293625.293633},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/RiepeS98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/ShiB98,
author = {C.{-}J. Richard Shi and
Janusz A. Brzozowski},
title = {Cluster-cover a theoretical framework for a class of {VLSI-CAD} optimization
problems},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {3},
number = {1},
pages = {76--107},
year = {1998},
url = {https://doi.org/10.1145/270580.270584},
doi = {10.1145/270580.270584},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/ShiB98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/SuHLL98,
author = {Alan Su and
Yu{-}Chin Hsu and
Ta{-}Yung Liu and
Mike Tien{-}Chien Lee},
title = {Eliminating false loops caused by sharing in control path},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {3},
number = {3},
pages = {487--495},
year = {1998},
url = {https://doi.org/10.1145/293625.293635},
doi = {10.1145/293625.293635},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/SuHLL98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/TiruvuriC98,
author = {Giri Tiruvuri and
Moon Chung},
title = {Estimation of lower bounds in scheduling algorithms for high-level
synthesis},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {3},
number = {2},
pages = {162--180},
year = {1998},
url = {https://doi.org/10.1145/290833.290839},
doi = {10.1145/290833.290839},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/TiruvuriC98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/VahidLH98,
author = {Frank Vahid and
Thuy Dm Le and
Yu{-}Chin Hsu},
title = {Functional partitioning improvements over structural partitioning
for packaging constraints and synthesis: tool performance},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {3},
number = {2},
pages = {181--208},
year = {1998},
url = {https://doi.org/10.1145/290833.290841},
doi = {10.1145/290833.290841},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/VahidLH98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/WangAZ98,
author = {Li{-}C. Wang and
Magdy S. Abadir and
Jing Zeng},
title = {On measuring the effectiveness of various design validation approaches
for PowerPC microprocessor embedded arrays},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {3},
number = {4},
pages = {524--532},
year = {1998},
url = {https://doi.org/10.1145/296333.296335},
doi = {10.1145/296333.296335},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/WangAZ98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/ZhouW98,
author = {Hai Zhou and
D. F. Wong},
title = {Optimal river routing with crosstalk constraints},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {3},
number = {3},
pages = {496--514},
year = {1998},
url = {https://doi.org/10.1145/293625.293636},
doi = {10.1145/293625.293636},
timestamp = {Wed, 16 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/ZhouW98.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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