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@article{DBLP:journals/tvlsi/AbulafiaK05,
author = {Y. Abulafia and
Avner Kornfeld},
title = {Estimation of {FMAX} and {ISB} in microprocessors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {10},
pages = {1205--1209},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.859469},
doi = {10.1109/TVLSI.2005.859469},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AbulafiaK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AgarwalPMDR05,
author = {Amit Agarwal and
Bipul Chandra Paul and
Hamid Mahmoodi{-}Meimand and
Animesh Datta and
Kaushik Roy},
title = {A process-tolerant cache architecture for improved yield in nanoscale
technologies},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {1},
pages = {27--38},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.840407},
doi = {10.1109/TVLSI.2004.840407},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AgarwalPMDR05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AndoTW05,
author = {Hisashige Ando and
Nestoras Tzartzanis and
William W. Walker},
title = {A Case Study: Power and Performance Improvement of a Chip Multiprocessor
for Transaction Processing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {7},
pages = {865--868},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.850120},
doi = {10.1109/TVLSI.2005.850120},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AndoTW05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/AshrafiA05,
author = {Ashkan Ashrafi and
Reza R. Adhami},
title = {Comments on "A 13-bit resolution ROM-less direct digital frequency
synthesizer based on a trigonometric quadruple angle formula"},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {9},
pages = {1096--1098},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.857155},
doi = {10.1109/TVLSI.2005.857155},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/AshrafiA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BachmannH05,
author = {W. W. Bachmann and
Sorin A. Huss},
title = {Efficient algorithms for multilevel power estimation of {VLSI} circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {2},
pages = {238--254},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.840769},
doi = {10.1109/TVLSI.2004.840769},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BachmannH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BaegC05,
author = {Sanghyeon Baeg and
Sung Soo Chung},
title = {Analytical test buffer design for differential signaling {I/O} buffers
by error syndrome analysis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {3},
pages = {370--383},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.842899},
doi = {10.1109/TVLSI.2004.842899},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BaegC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BakerP05,
author = {Zachary K. Baker and
Viktor K. Prasanna},
title = {A computationally efficient engine for flexible intrusion detection},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {10},
pages = {1179--1189},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.859472},
doi = {10.1109/TVLSI.2005.859472},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BakerP05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BhuniaMGMR05,
author = {Swarup Bhunia and
Hamid Mahmoodi{-}Meimand and
Debjyoti Ghosh and
Saibal Mukhopadhyay and
Kaushik Roy},
title = {Low-power scan design using first-level supply gating},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {3},
pages = {384--395},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.842885},
doi = {10.1109/TVLSI.2004.842885},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BhuniaMGMR05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/BhuniaR05,
author = {Swarup Bhunia and
Kaushik Roy},
title = {A novel wavelet transform-based transient current analysis for fault
detection and localization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {4},
pages = {503--507},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.842880},
doi = {10.1109/TVLSI.2004.842880},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/BhuniaR05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Burgess05,
author = {Neil Burgess},
title = {Prenormalization rounding in {IEEE} floating-point operations using
a flagged prefix adder},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {2},
pages = {266--277},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.840764},
doi = {10.1109/TVLSI.2004.840764},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Burgess05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CaoHSKH05,
author = {Yu Cao and
Xuejue Huang and
Dennis Sylvester and
Tsu{-}Jae King and
Chenming Hu},
title = {Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital
and {RF} design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {1},
pages = {158--162},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.840399},
doi = {10.1109/TVLSI.2004.840399},
timestamp = {Fri, 07 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/CaoHSKH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CaoYHS05,
author = {Yu Cao and
Xiaodong Yang and
Xuejue Huang and
Dennis Sylvester},
title = {Switch-factor based loop {RLC} modeling for efficient timing analysis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {9},
pages = {1072--1078},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.857175},
doi = {10.1109/TVLSI.2005.857175},
timestamp = {Fri, 07 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/CaoYHS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CenturelliGGMMPST05,
author = {Francesco Centurelli and
Alessandro Golfarelli and
Jesus Guinea and
Leonardo Masini and
Damiana Morigi and
Massimo Pozzoni and
Giuseppe Scotti and
Alessandro Trifiletti},
title = {A 10-Gb/s {CMU/CDR} chip-set in SiGe BiCMOS commercial technology
with multistandard capability},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {2},
pages = {191--200},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.840784},
doi = {10.1109/TVLSI.2004.840784},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/CenturelliGGMMPST05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChabiniW05,
author = {Noureddine Chabini and
Wayne H. Wolf},
title = {Unification of scheduling, binding, and retiming to reduce power consumption
under timings and resources constraints},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {10},
pages = {1113--1126},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.859482},
doi = {10.1109/TVLSI.2005.859482},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChabiniW05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChangGZ05,
author = {Chip{-}Hong Chang and
Jiangmin Gu and
Mingyan Zhang},
title = {A review of 0.18-{\(\mu\)}m full adder performances for tree structured
arithmetic circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {6},
pages = {686--695},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.848806},
doi = {10.1109/TVLSI.2005.848806},
timestamp = {Tue, 27 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChangGZ05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChatterjeeS05,
author = {Bhaskar Chatterjee and
Manoj Sachdev},
title = {Design of a 1.7-GHz low-power delay-fault-testable 32-b {ALU} in 180-nm
{CMOS} technology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {11},
pages = {1296--1304},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.859563},
doi = {10.1109/TVLSI.2005.859563},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChatterjeeS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChattopadhyayZ05,
author = {Atanu Chattopadhyay and
Zeljko Zilic},
title = {{GALDS:} a complete framework for designing multiclock ASICs and SoCs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {6},
pages = {641--654},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.848825},
doi = {10.1109/TVLSI.2005.848825},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChattopadhyayZ05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChaturvediH05,
author = {Rishi Chaturvedi and
Jiang Hu},
title = {An efficient merging scheme for prescribed skew clock routing},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {6},
pages = {750--754},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.848821},
doi = {10.1109/TVLSI.2005.848821},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChaturvediH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Chen05,
author = {T. Chen},
title = {On the impact of on-chip inductance on signal nets under the influence
of power grid noise},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {3},
pages = {339--348},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.842893},
doi = {10.1109/TVLSI.2004.842893},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Chen05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenMBR05,
author = {Qikai Chen and
Hamid Mahmoodi{-}Meimand and
Swarup Bhunia and
Kaushik Roy},
title = {Efficient testing of {SRAM} with optimized march sequences and a novel
{DFT} technique for emerging failures due to process variations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {11},
pages = {1286--1295},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.859565},
doi = {10.1109/TVLSI.2005.859565},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenMBR05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChenRK05,
author = {Yiran Chen and
Kaushik Roy and
Cheng{-}Kok Koh},
title = {Current demand balancing: a technique for minimization of current
surge in high performance clock-gated microprocessors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {1},
pages = {75--85},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.840404},
doi = {10.1109/TVLSI.2004.840404},
timestamp = {Mon, 04 Jul 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChenRK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CheresizJVW05,
author = {Dmitry Cheresiz and
Ben H. H. Juurlink and
Stamatis Vassiliadis and
Harry A. G. Wijshoff},
title = {The {CSI} multimedia architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {1},
pages = {1--13},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.840415},
doi = {10.1109/TVLSI.2004.840415},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/CheresizJVW05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/CheungTLC05,
author = {Ray C. C. Cheung and
N. J. Telle and
Wayne Luk and
Peter Y. K. Cheung},
title = {Customizable elliptic curve cryptosystems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {9},
pages = {1048--1059},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.857179},
doi = {10.1109/TVLSI.2005.857179},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/CheungTLC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChongGC05,
author = {Kwen{-}Siong Chong and
Bah{-}Hwee Gwee and
Joseph Sylvester Chang},
title = {A micropower low-voltage multiplier with reduced spurious switching},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {2},
pages = {255--265},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.840765},
doi = {10.1109/TVLSI.2004.840765},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChongGC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChowdhuryC05,
author = {Princey Chowdhury and
Chaitali Chakrabarti},
title = {Static task-scheduling algorithms for battery-powered {DVS} systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {2},
pages = {226--237},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.840771},
doi = {10.1109/TVLSI.2004.840771},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ChowdhuryC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ConstantinidesCL05,
author = {George A. Constantinides and
Peter Y. K. Cheung and
Wayne Luk},
title = {Optimum and heuristic synthesis of multiple word-length architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {1},
pages = {39--57},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.840398},
doi = {10.1109/TVLSI.2004.840398},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ConstantinidesCL05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DandalisP05,
author = {Andreas Dandalis and
Viktor K. Prasanna},
title = {Configuration compression for FPGA-based embedded systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {12},
pages = {1394--1398},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.862721},
doi = {10.1109/TVLSI.2005.862721},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DandalisP05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DavoodiS05,
author = {Azadeh Davoodi and
Ankur Srivastava},
title = {Power-driven simultaneous resource binding and floorplanning: a probabilistic
approach},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {8},
pages = {934--942},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.853618},
doi = {10.1109/TVLSI.2005.853618},
timestamp = {Thu, 18 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DavoodiS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DegalahalLNKI05,
author = {Vijay Degalahal and
Lin Li and
Narayanan Vijaykrishnan and
Mahmut T. Kandemir and
Mary Jane Irwin},
title = {Soft errors issues in low-power caches},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {10},
pages = {1157--1166},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.859474},
doi = {10.1109/TVLSI.2005.859474},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DegalahalLNKI05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DengM05,
author = {Yangdong Deng and
Wojciech P. Maly},
title = {2.5-dimensional {VLSI} system integration},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {6},
pages = {668--677},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.848814},
doi = {10.1109/TVLSI.2005.848814},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DengM05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DeodharD05,
author = {Vinita V. Deodhar and
Jeffrey A. Davis},
title = {Optimization of throughput performance for low-power {VLSI} interconnects},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {3},
pages = {308--318},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.842898},
doi = {10.1109/TVLSI.2004.842898},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DeodharD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DinhH05,
author = {Anh Dinh and
Xiao Hu},
title = {A hardware-efficient technique to implement a trellis code modulation
decoder},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {6},
pages = {745--750},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.848822},
doi = {10.1109/TVLSI.2005.848822},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DinhH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DirilDCS05,
author = {Abdulkadir Utku Diril and
Yuvraj Singh Dhillon and
Abhijit Chatterjee and
Adit D. Singh},
title = {Level-shifter free design of low power dual supply voltage {CMOS}
circuits using dual threshold voltages},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {9},
pages = {1103--1107},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.857149},
doi = {10.1109/TVLSI.2005.857149},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DirilDCS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/DobkinPG05,
author = {Rostislav (Reuven) Dobkin and
Michael Peleg and
Ran Ginosar},
title = {Parallel interleaver design and {VLSI} architecture for low-latency
{MAP} turbo decoders},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {4},
pages = {427--438},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.842916},
doi = {10.1109/TVLSI.2004.842916},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/DobkinPG05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/EfthymiouBE05,
author = {Aristides Efthymiou and
John Bainbridge and
Douglas A. Edwards},
title = {Test pattern generation and partial-scan methodology for an asynchronous
SoC interconnect},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {12},
pages = {1384--1393},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.862722},
doi = {10.1109/TVLSI.2005.862722},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/EfthymiouBE05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/EganM05,
author = {Tom Egan and
Samiha Mourad},
title = {Design-for-testability for embedded delay-locked loops},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {8},
pages = {984--988},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.853622},
doi = {10.1109/TVLSI.2005.853622},
timestamp = {Wed, 10 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/EganM05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/El-MoursyF05,
author = {Magdy A. El{-}Moursy and
Eby G. Friedman},
title = {Shielding effect of on-chip interconnect inductance},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {3},
pages = {396--400},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.842315},
doi = {10.1109/TVLSI.2004.842315},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/El-MoursyF05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/El-MoursyF05a,
author = {Magdy A. El{-}Moursy and
Eby G. Friedman},
title = {Exponentially tapered H-tree clock distribution networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {8},
pages = {971--975},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.853602},
doi = {10.1109/TVLSI.2005.853602},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/El-MoursyF05a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ElgamelKB05,
author = {Mohamed A. Elgamel and
Ashok Kumar and
Magdy A. Bayoumi},
title = {Efficient shield insertion for inductive noise reduction in nanometer
technologies},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {3},
pages = {401--405},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.842882},
doi = {10.1109/TVLSI.2004.842882},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ElgamelKB05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Favalli05,
author = {Michele Favalli},
title = {A fuzzy model for path delay fault detection},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {8},
pages = {943--956},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.853608},
doi = {10.1109/TVLSI.2005.853608},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Favalli05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/FischerDCG05,
author = {Viktor Fischer and
Milos Drutarovsk{\'{y}} and
Pawel Chodowiec and
F. Gramain},
title = {InvMixColumn decomposition and multilevel resource sharing in {AES}
implementations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {8},
pages = {989--992},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.853606},
doi = {10.1109/TVLSI.2005.853606},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/FischerDCG05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GonciariAN05,
author = {Paul Theo Gonciari and
Bashir M. Al{-}Hashimi and
Nicola Nicolici},
title = {Synchronization overhead in {SOC} compressed test},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {1},
pages = {140--152},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.834238},
doi = {10.1109/TVLSI.2004.834238},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GonciariAN05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/GuiKWMWWHK05,
author = {Ping Gui and
Fouad E. Kiamilev and
Xiaoqing Wang and
Michael J. MacFadden and
Xingle Wang and
Nick Waite and
Michael W. Haney and
Charlie Kuznia},
title = {A Source-Synchronous Double-Data-Rate Parallel Optical Transceiver
{IC}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {7},
pages = {833--842},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.850101},
doi = {10.1109/TVLSI.2005.850101},
timestamp = {Thu, 14 Jan 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/GuiKWMWWHK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HabalMF05,
author = {Husni M. Habal and
Kartikeya Mayaram and
Terri S. Fiez},
title = {Accurate and efficient simulation of synchronous digital switching
noise in systems on a chip},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {3},
pages = {330--338},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.842894},
doi = {10.1109/TVLSI.2004.842894},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HabalMF05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HallschmidW05,
author = {Peter Hallschmid and
Steven J. E. Wilton},
title = {Routing architecture optimizations for high-density embedded programmable
{IP} cores},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {11},
pages = {1320--1324},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.859561},
doi = {10.1109/TVLSI.2005.859561},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HallschmidW05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HassanAE05,
author = {Hassan Hassan and
Mohab Anis and
Mohamed I. Elmasry},
title = {{MOS} current mode circuits: analysis, design, and variability},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {8},
pages = {885--898},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.853609},
doi = {10.1109/TVLSI.2005.853609},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HassanAE05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HassounKPS05,
author = {Soha Hassoun and
Murali Kudlugi and
Duaine Pryor and
Charles Selvidge},
title = {A transaction-based unified architecture for simulation and emulation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {2},
pages = {278--287},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.840763},
doi = {10.1109/TVLSI.2004.840763},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HassounKPS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Hiasat05,
author = {Ahmad A. Hiasat},
title = {{VLSI} implementation of new arithmetic residue to binary decoders},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {1},
pages = {153--158},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.840400},
doi = {10.1109/TVLSI.2004.840400},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Hiasat05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuaQ05,
author = {Shaoxiong Hua and
Gang Qu},
title = {Voltage Setup Problem for Embedded Systems With Multiple Voltages},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {7},
pages = {869--872},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.850122},
doi = {10.1109/TVLSI.2005.850122},
timestamp = {Tue, 14 Dec 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HuaQ05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/HuangTL05,
author = {Jing Huang and
Mehdi Baradaran Tahoori and
Fabrizio Lombardi},
title = {Fault Tolerance of Switch Blocks and Switch Block Arrays in {FPGA}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {7},
pages = {794--807},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.850090},
doi = {10.1109/TVLSI.2005.850090},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/HuangTL05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/IraniSSG05,
author = {Sandy Irani and
Gaurav Singh and
Sandeep K. Shukla and
Rajesh K. Gupta},
title = {An overview of the competitive and adversarial approaches to designing
dynamic power management strategies},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {12},
pages = {1349--1361},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.862725},
doi = {10.1109/TVLSI.2005.862725},
timestamp = {Wed, 02 Nov 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/IraniSSG05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JangCP05,
author = {Ju{-}wook Jang and
Seonil B. Choi and
Viktor K. Prasanna},
title = {Energy- and time-efficient matrix multiplication on FPGAs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {11},
pages = {1305--1319},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.859562},
doi = {10.1109/TVLSI.2005.859562},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JangCP05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JigangSS05,
author = {Wu Jigang and
Thambipillai Srikanthan and
Heiko Schr{\"{o}}der},
title = {Efficient reconfigurable techniques for {VLSI} arrays with 6-port
switches},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {8},
pages = {976--979},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.853603},
doi = {10.1109/TVLSI.2005.853603},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JigangSS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/JoshiD05,
author = {Ajay Joshi and
Jeffrey A. Davis},
title = {Wave-pipelined multiplexed {(WPM)} routing for gigascale integration
{(GSI)}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {8},
pages = {899--910},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.853611},
doi = {10.1109/TVLSI.2005.853611},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/JoshiD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KandemirICK05,
author = {Mahmut T. Kandemir and
Mary Jane Irwin and
Guangyu Chen and
Ibrahim Kolcu},
title = {Compiler-guided leakage optimization for banked scratch-pad memories},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {10},
pages = {1136--1146},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.859478},
doi = {10.1109/TVLSI.2005.859478},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KandemirICK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KarandikarS05,
author = {Shrirang K. Karandikar and
Sachin S. Sapatnekar},
title = {Fast comparisons of circuit implementations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {12},
pages = {1329--1339},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.862727},
doi = {10.1109/TVLSI.2005.862727},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KarandikarS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KaulSAK05,
author = {Himanshu Kaul and
Dennis Sylvester and
Mark A. Anders and
Ram Krishnamurthy},
title = {Design and analysis of spatial encoding circuits for peak power reduction
in on-chip buses},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {11},
pages = {1225--1238},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.859589},
doi = {10.1109/TVLSI.2005.859589},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KaulSAK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KhandelwalDS05,
author = {Vishal Khandelwal and
Azadeh Davoodi and
Ankur Srivastava},
title = {Simultaneous V\({}_{\mbox{t}}\) selection and assignment for leakage
optimization},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {6},
pages = {762--765},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.844304},
doi = {10.1109/TVLSI.2005.844304},
timestamp = {Thu, 18 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KhandelwalDS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KhouriLJ05,
author = {Kamal S. Khouri and
Ganesh Lakshminarayana and
Niraj K. Jha},
title = {Memory binding for performance optimization of control-flow intensive
behavioral descriptions},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {5},
pages = {513--524},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.844292},
doi = {10.1109/TVLSI.2005.844292},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KhouriLJ05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimBM05,
author = {Nam Sung Kim and
David T. Blaauw and
Trevor N. Mudge},
title = {Quantitative analysis and optimization techniques for on-chip cache
leakage power},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {10},
pages = {1147--1156},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.859476},
doi = {10.1109/TVLSI.2005.859476},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimBM05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimHK05,
author = {Chang Hoon Kim and
Chun Pyo Hong and
Soonhak Kwon},
title = {A digit-serial multiplier for finite field GF(2\({}^{\mbox{m}}\))},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {4},
pages = {476--483},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.842923},
doi = {10.1109/TVLSI.2004.842923},
timestamp = {Wed, 28 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KimHK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimIH05,
author = {Sungchan Kim and
Chaeseok Im and
Soonhoi Ha},
title = {Schedule-aware performance estimation of communication architecture
for efficient design space exploration},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {5},
pages = {539--552},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.842912},
doi = {10.1109/TVLSI.2004.842912},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimIH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimKMR05,
author = {Chris H. Kim and
Jae{-}Joon Kim and
Saibal Mukhopadhyay and
Kaushik Roy},
title = {A forward body-biased low-leakage {SRAM} cache: device, circuit and
architecture considerations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {3},
pages = {349--357},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.842903},
doi = {10.1109/TVLSI.2004.842903},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimKMR05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KimSC05,
author = {Daehong Kim and
Dongwan Shin and
Kiyoung Choi},
title = {Pipelining with common operands for power-efficient linear systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {9},
pages = {1023--1034},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.857146},
doi = {10.1109/TVLSI.2005.857146},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KimSC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KoobLSBECM05,
author = {John C. Koob and
Daniel A. Leder and
Raymond J. Sung and
Tyler L. Brandon and
Duncan G. Elliott and
Bruce F. Cockburn and
Lisa G. McIlrath},
title = {Design of a 3-D fully depleted {SOI} computational {RAM}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {3},
pages = {358--369},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.842890},
doi = {10.1109/TVLSI.2004.842890},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KoobLSBECM05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KosunenVWH05,
author = {Marko Kosunen and
Jouko Vankka and
Mikko Waltari and
Kari Halonen},
title = {A multicarrier {QAM} modulator for {WCDMA} base-station with on-chip
{D/A} converter},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {2},
pages = {181--190},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.840778},
doi = {10.1109/TVLSI.2004.840778},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/KosunenVWH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/KwonK05,
author = {Young{-}Su Kwon and
C.{-}M. Kyung},
title = {ATOMi: An Algorithm for Circuit Partitioning Into Multiple FPGAs Using
Time-Multiplexed, Off-Chip, Multicasting Interconnection Architecture},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {7},
pages = {861--864},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.850117},
doi = {10.1109/TVLSI.2005.850117},
timestamp = {Sun, 08 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/KwonK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LakshminarayananV05,
author = {Gopalakrishnan Lakshminarayanan and
B. Venkataramani},
title = {Optimization Techniques for FPGA-Based Wave-Pipelined {DSP} Blocks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {7},
pages = {783--793},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.850086},
doi = {10.1109/TVLSI.2005.850086},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LakshminarayananV05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeLVZL05,
author = {Dong{-}U Lee and
Wayne Luk and
John D. Villasenor and
Guanglie Zhang and
Philip Heng Wai Leong},
title = {A hardware Gaussian noise generator using the Wallace method},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {8},
pages = {911--920},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.853615},
doi = {10.1109/TVLSI.2005.853615},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeLVZL05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeNCKD05,
author = {Seungbae Lee and
Gi{-}Joon Nam and
Junseok Chae and
Hanseup Kim and
Alan J. Drake},
title = {Two-dimensional position detection system with {MEMS} accelerometers,
readout circuitry, and microprocessor for padless mouse applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {10},
pages = {1167--1178},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.859473},
doi = {10.1109/TVLSI.2005.859473},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeNCKD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LeeSS05,
author = {Seok{-}Jun Lee and
Naresh R. Shanbhag and
Andrew C. Singer},
title = {Area-efficient high-throughput {MAP} decoder architectures},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {8},
pages = {921--933},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.853604},
doi = {10.1109/TVLSI.2005.853604},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LeeSS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LekatsasHW05,
author = {Haris Lekatsas and
J{\"{o}}rg Henkel and
Wayne H. Wolf},
title = {Approximate arithmetic coding for bus transition reduction in low
power designs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {6},
pages = {696--707},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.848803},
doi = {10.1109/TVLSI.2005.848803},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LekatsasHW05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Li05,
author = {James Chien{-}Mo Li},
title = {Diagnosis of single stuck-at faults and multiple timing faults in
scan chains},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {6},
pages = {708--718},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.848800},
doi = {10.1109/TVLSI.2005.848800},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Li05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiCRV05,
author = {Hai Li and
Chen{-}Yong Cher and
Kaushik Roy and
T. N. Vijaykumar},
title = {Combined circuit and architectural level variable supply-voltage scaling
for low power},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {5},
pages = {564--576},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.844295},
doi = {10.1109/TVLSI.2005.844295},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiCRV05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiYHW05,
author = {Jin{-}Fu Li and
Jen{-}Chieh Yeh and
Rei{-}Fu Huang and
Cheng{-}Wen Wu},
title = {A built-in self-repair design for RAMs with 2-D redundancy},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {6},
pages = {742--745},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.848824},
doi = {10.1109/TVLSI.2005.848824},
timestamp = {Tue, 17 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LiYHW05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiaoBH05,
author = {Weiping Liao and
Joseph M. Basile and
Lei He},
title = {Microarchitecture-level leakage reduction with data retention},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {11},
pages = {1324--1328},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.859560},
doi = {10.1109/TVLSI.2005.859560},
timestamp = {Mon, 13 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiaoBH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LimLGSDD05,
author = {Daihyun Lim and
Jae W. Lee and
Blaise Gassend and
G. Edward Suh and
Marten van Dijk and
Srinivas Devadas},
title = {Extracting secret keys from integrated circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {10},
pages = {1200--1205},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.859470},
doi = {10.1109/TVLSI.2005.859470},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LimLGSDD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinC05,
author = {Jai{-}Ming Lin and
Yao{-}Wen Chang},
title = {{TCG:} {A} transitive closure graph-based representation for general
floorplans},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {2},
pages = {288--292},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.840760},
doi = {10.1109/TVLSI.2004.840760},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LinC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinLH05,
author = {Yan Lin and
Fei Li and
Lei He},
title = {Circuits and architectures for field programmable gate array with
configurable supply voltage},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {9},
pages = {1035--1047},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.857180},
doi = {10.1109/TVLSI.2005.857180},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LinLH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LinZ05,
author = {Chuan Lin and
Hai Zhou},
title = {Wire retiming as fixpoint computation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {12},
pages = {1340--1348},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.862726},
doi = {10.1109/TVLSI.2005.862726},
timestamp = {Wed, 16 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LinZ05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LitvinM05,
author = {Miguel Eduardo Litvin and
Samiha Mourad},
title = {Self-reset logic for fast arithmetic applications},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {4},
pages = {462--475},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.842921},
doi = {10.1109/TVLSI.2004.842921},
timestamp = {Tue, 12 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/LitvinM05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LiuC05,
author = {Chunsheng Liu and
Krishnendu Chakrabarty},
title = {Design and analysis of compact dictionaries for diagnosis in scan-BIST},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {8},
pages = {979--984},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.853624},
doi = {10.1109/TVLSI.2005.853624},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LiuC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/LuSH05,
author = {Shyue{-}Kung Lu and
Jen{-}Sheng Shih and
Shih{-}Chang Huang},
title = {Design-for-testability and fault-tolerant techniques for {FFT} processors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {6},
pages = {732--741},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.844306},
doi = {10.1109/TVLSI.2005.844306},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/LuSH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MaKP05,
author = {Fred Ma and
John P. Knight and
Calvin Plett},
title = {Physical resource binding for a coarse-grain reconfigurable array
using evolutionary algorithms},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {5},
pages = {553--563},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.844286},
doi = {10.1109/TVLSI.2005.844286},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MaKP05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MaslovDM05,
author = {Dmitri Maslov and
Gerhard W. Dueck and
D. Michael Miller},
title = {Synthesis of Fredkin-Toffoli reversible networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {6},
pages = {765--769},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.844284},
doi = {10.1109/TVLSI.2005.844284},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MaslovDM05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MichaelT05,
author = {Maria K. Michael and
Spyros Tragoudas},
title = {Function-based compact test pattern generation for path delay faults},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {8},
pages = {996--1001},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.853607},
doi = {10.1109/TVLSI.2005.853607},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MichaelT05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MohantyRN05,
author = {Saraju P. Mohanty and
Nagarajan Ranganathan and
Ravi Namballa},
title = {A {VLSI} architecture for watermarking in a secure still digital camera
(S\({}^{\mbox{2}}\)DC) design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {7},
pages = {808--818},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.850095},
doi = {10.1109/TVLSI.2005.850095},
timestamp = {Wed, 28 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MohantyRN05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MohantyRN05a,
author = {Saraju P. Mohanty and
Nagarajan Ranganathan and
Ravi Namballa},
title = {A {VLSI} architecture for visible watermarking in a secure still digital
camera (S\({}^{\mbox{2}}\)/DC) design (Corrected)*},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {8},
pages = {1002--1012},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.857991},
doi = {10.1109/TVLSI.2005.857991},
timestamp = {Wed, 28 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/MohantyRN05a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MooreMB05,
author = {Brian Moore and
Martin Margala and
Christopher J. Backhouse},
title = {Design of wireless on-wafer submicron characterization system},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {2},
pages = {169--180},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.840780},
doi = {10.1109/TVLSI.2004.840780},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MooreMB05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/MoshovosFNA05,
author = {Andreas Moshovos and
Babak Falsafi and
Farid N. Najm and
Navid Azizi},
title = {A Case for Asymmetric-Cell Cache Memories},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {7},
pages = {877--881},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.850127},
doi = {10.1109/TVLSI.2005.850127},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/MoshovosFNA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/NedovicO05,
author = {Nikola Nedovic and
Vojin G. Oklobdzija},
title = {Dual-edge triggered storage elements and clocking strategy for low-power
systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {5},
pages = {577--590},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.844302},
doi = {10.1109/TVLSI.2005.844302},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/NedovicO05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/OklobdzijaZDMK05,
author = {Vojin G. Oklobdzija and
Bart R. Zeydel and
Hoang Q. Dao and
Sanu Mathew and
Ram Krishnamurthy},
title = {Comparison of high-performance {VLSI} adders in the energy-delay space},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {6},
pages = {754--758},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.848819},
doi = {10.1109/TVLSI.2005.848819},
timestamp = {Fri, 25 Feb 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/OklobdzijaZDMK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/OldridgeW05,
author = {Steven W. Oldridge and
Steven J. E. Wilton},
title = {A novel {FPGA} architecture supporting wide, shallow memories},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {6},
pages = {758--762},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.848817},
doi = {10.1109/TVLSI.2005.848817},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/OldridgeW05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/OlivieriST05,
author = {Mauro Olivieri and
Giuseppe Scotti and
Alessandro Trifiletti},
title = {A novel yield optimization technique for digital {CMOS} circuits design
by means of process parameters run-time estimation and body bias active
control},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {5},
pages = {630--638},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.844290},
doi = {10.1109/TVLSI.2005.844290},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/OlivieriST05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ParameswaranH05,
author = {Sri Parameswaran and
J{\"{o}}rg Henkel},
title = {Instruction code mapping for performance increase and energy reduction
in embedded computer systems},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {4},
pages = {498--502},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.842936},
doi = {10.1109/TVLSI.2004.842936},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ParameswaranH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/Parhi05,
author = {Keshab K. Parhi},
title = {Design of multigigabit multiplexer-loop-based decision feedback equalizers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {4},
pages = {489--493},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.842935},
doi = {10.1109/TVLSI.2004.842935},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/Parhi05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PengL05,
author = {Dongming Peng and
Mi Lu},
title = {Non-RAM-based architectural designs of wavelet-based digital systems
based on novel nonlinear {I/O} data space transformations},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {1},
pages = {58--74},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.840405},
doi = {10.1109/TVLSI.2004.840405},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PengL05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PengL05a,
author = {Dongming Peng and
Mi Lu},
title = {On exploring inter-iteration parallelism within rate-balanced multirate
multidimensional {DSP} algorithms},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {1},
pages = {106--125},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.840401},
doi = {10.1109/TVLSI.2004.840401},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PengL05a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/PomeranzR05,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Autoscan: a scan design without external scan inputs or outputs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {9},
pages = {1087--1095},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.857157},
doi = {10.1109/TVLSI.2005.857157},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/PomeranzR05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RaghunathanPSG05,
author = {Vijay Raghunathan and
Cristiano Pereira and
Mani B. Srivastava and
Rajesh K. Gupta},
title = {Energy-aware wireless systems with adaptive power-fidelity tradeoffs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {2},
pages = {211--225},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.840773},
doi = {10.1109/TVLSI.2004.840773},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RaghunathanPSG05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RaoDBS05,
author = {Rajeev R. Rao and
Harmander Deogun and
David T. Blaauw and
Dennis Sylvester},
title = {Bus encoding for total power reduction using a leakage-aware buffer
configuration},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {12},
pages = {1376--1383},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.862718},
doi = {10.1109/TVLSI.2005.862718},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RaoDBS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/RaychowdhuryPBR05,
author = {Arijit Raychowdhury and
Bipul Chandra Paul and
Swarup Bhunia and
Kaushik Roy},
title = {Computing with subthreshold leakage: device/circuit/architecture co-design
for ultralow-power subthreshold operation},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {11},
pages = {1213--1224},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.859590},
doi = {10.1109/TVLSI.2005.859590},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/RaychowdhuryPBR05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SafarianYH05,
author = {Amin Q. Safarian and
Ahmad Yazdi and
Payam Heydari},
title = {Design and analysis of an ultrawide-band distributed {CMOS} mixer},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {5},
pages = {618--629},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.844288},
doi = {10.1109/TVLSI.2005.844288},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SafarianYH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SaraswatAN05,
author = {Dharmendra Saraswat and
Ramachandra Achar and
Michel S. Nakhla},
title = {Global Passivity Enforcement Algorithm for Macromodels of Interconnect
Subnetworks Characterized by Tabulated Data},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {7},
pages = {819--832},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.850098},
doi = {10.1109/TVLSI.2005.850098},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SaraswatAN05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SchmitC05,
author = {Herman Schmit and
Vikas Chandra},
title = {Layout techniques for {FPGA} switch blocks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {1},
pages = {96--105},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.840402},
doi = {10.1109/TVLSI.2004.840402},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SchmitC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SharmaBAXFM05,
author = {Ajit Sharma and
Patrick Birrer and
Sasi Kumar Arunachalam and
Chenggang Xu and
Terri S. Fiez and
Kartikeya Mayaram},
title = {Accurate Prediction of Substrate Parasitics in Heavily Doped {CMOS}
Processes Using a Calibrated Boundary Element Solver},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {7},
pages = {843--851},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.850106},
doi = {10.1109/TVLSI.2005.850106},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SharmaBAXFM05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShelarS05,
author = {Rupesh S. Shelar and
Sachin S. Sapatnekar},
title = {{BDD} decomposition for delay oriented pass transistor logic synthesis},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {8},
pages = {957--970},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.853601},
doi = {10.1109/TVLSI.2005.853601},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ShelarS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ShiMYDL05,
author = {Xiaomeng Shi and
Jianguo Ma and
Kiat Seng Yeo and
Manh Anh Do and
Erping Li},
title = {Equivalent circuit model of on-wafer {CMOS} interconnects for RFICs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {9},
pages = {1060--1071},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.857177},
doi = {10.1109/TVLSI.2005.857177},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ShiMYDL05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SridharaS05,
author = {Srinivasa R. Sridhara and
Naresh R. Shanbhag},
title = {Coding for system-on-chip networks: a unified framework},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {6},
pages = {655--667},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.848816},
doi = {10.1109/TVLSI.2005.848816},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SridharaS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/StaszewskiSWJHKLMB05,
author = {Robert Bogdan Staszewski and
Roman Staszewski and
John L. Wallberg and
Tom Jung and
Chih{-}Ming Hung and
Jinseok Koh and
Dirk Leipold and
Kenneth Maggio and
Poras T. Balsara},
title = {SoC with an integrated {DSP} and a 2.4-GHz {RF} transmitter},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {11},
pages = {1253--1265},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.859587},
doi = {10.1109/TVLSI.2005.859587},
timestamp = {Thu, 06 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/StaszewskiSWJHKLMB05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/StrolloCNP05,
author = {Antonio G. M. Strollo and
Davide De Caro and
Ettore Napoli and
Nicola Petra},
title = {A novel high-speed sense-amplifier-based flip-flop},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {11},
pages = {1266--1274},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.859586},
doi = {10.1109/TVLSI.2005.859586},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/StrolloCNP05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SultaniaSS05,
author = {Anup Kumar Sultania and
Dennis Sylvester and
Sachin S. Sapatnekar},
title = {Gate oxide leakage and delay tradeoffs for dual-T\({}_{\mbox{ox}}\)
circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {12},
pages = {1362--1375},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.862723},
doi = {10.1109/TVLSI.2005.862723},
timestamp = {Wed, 28 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SultaniaSS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SunZ05,
author = {Fei Sun and
Tong Zhang},
title = {Parallel high-throughput limited search trellis decoder {VLSI} design},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {9},
pages = {1013--1022},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.857181},
doi = {10.1109/TVLSI.2005.857181},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/SunZ05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SzymanskiWG05,
author = {Ted H. Szymanski and
Honglin Wu and
Amir Gourgy},
title = {Power complexity of multiplexer-based optoelectronic crossbar switches},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {5},
pages = {604--617},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.844285},
doi = {10.1109/TVLSI.2005.844285},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SzymanskiWG05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TailleferR05,
author = {Christopher S. Taillefer and
Gordon W. Roberts},
title = {Reducing Measurement Uncertainty in a DSP-Based Mixed-Signal Test
Environment Without Increasing Test Time},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {7},
pages = {852--860},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.850113},
doi = {10.1109/TVLSI.2005.850113},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TailleferR05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TalpesM05,
author = {Emil Talpes and
Diana Marculescu},
title = {Execution cache-based microarchitecture for power-efficient superscalar
processors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {1},
pages = {14--26},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.840406},
doi = {10.1109/TVLSI.2004.840406},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TalpesM05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TalpesM05a,
author = {Emil Talpes and
Diana Marculescu},
title = {Toward a multiple clock/voltage island design style for power-aware
processors},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {5},
pages = {591--603},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.844305},
doi = {10.1109/TVLSI.2005.844305},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TalpesM05a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TehranipoorNC05,
author = {Mohammad Tehranipoor and
Mehrdad Nourani and
Krishnendu Chakrabarty},
title = {Nine-coded compression technique for testing embedded cores in SoCs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {6},
pages = {719--731},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.844311},
doi = {10.1109/TVLSI.2005.844311},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TehranipoorNC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TessierJMNXB05,
author = {Russell Tessier and
David Jasinski and
Atul Maheshwari and
Aiyappan Natarajan and
Weifeng Xu and
Wayne P. Burleson},
title = {An energy-aware active smart card},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {10},
pages = {1190--1199},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.859471},
doi = {10.1109/TVLSI.2005.859471},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TessierJMNXB05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TessierSRGB05,
author = {Russell Tessier and
Sriram Swaminathan and
Ramaswamy Ramaswamy and
Dennis Goeckel and
Wayne P. Burleson},
title = {A reconfigurable, power-efficient adaptive Viterbi decoder},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {4},
pages = {484--488},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.842930},
doi = {10.1109/TVLSI.2004.842930},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TessierSRGB05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ThepayasuwanD05,
author = {Nattawut Thepayasuwan and
Alex Doboli},
title = {Layout conscious approach and bus architecture synthesis for hardware/software
codesign of systems on chip optimized for speed},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {5},
pages = {525--538},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.842910},
doi = {10.1109/TVLSI.2004.842910},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ThepayasuwanD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TingWC05,
author = {Lok{-}Kee Ting and
Roger F. Woods and
C. F. N. Cowan},
title = {Virtex {FPGA} implementation of a pipelined adaptive {LMS} predictor
for electronic support measures receivers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {1},
pages = {86--95},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.840403},
doi = {10.1109/TVLSI.2004.840403},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TingWC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TiwariZC05,
author = {Mayank Tiwari and
Yuming Zhu and
Chaitali Chakrabarti},
title = {Memory sub-banking scheme for high throughput MAP-based {SISO} decoders},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {4},
pages = {494--498},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.842937},
doi = {10.1109/TVLSI.2004.842937},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TiwariZC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/TugsinavisutHKKB05,
author = {Sunan Tugsinavisut and
Youpyo Hong and
Daewook Kim and
Kyeounsoo Kim and
Peter A. Beerel},
title = {Efficient asynchronous bundled-data pipelines for {DCT} matrix-vector
multiplication},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {4},
pages = {448--461},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.842908},
doi = {10.1109/TVLSI.2004.842908},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/TugsinavisutHKKB05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/VoyiatzisGP05,
author = {Ioannis Voyiatzis and
Dimitris Gizopoulos and
Antonis M. Paschalis},
title = {Accumulator-based test generation for robust sequential fault testing
in {DSP} cores in near-optimal time},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {9},
pages = {1079--1086},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.857159},
doi = {10.1109/TVLSI.2005.857159},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/VoyiatzisGP05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangLHCHCH05,
author = {Chua{-}Chin Wang and
Tzung{-}Je Lee and
Yu{-}Tzu Hsiao and
U. Fat Chio and
Chi{-}Chun Huang and
J.{-}J. J. Chin and
Ya{-}Hsin Hsueh},
title = {A multiparameter implantable microstimulator {SOC}},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {12},
pages = {1399--1402},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.862719},
doi = {10.1109/TVLSI.2005.862719},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangLHCHCH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangMPCD05,
author = {Hua Wang and
Miguel Miranda and
Antonis Papanikolaou and
Francky Catthoor and
Wim Dehaene},
title = {Variable tapered pareto buffer design and implementation allowing
run-time configuration for low-power embedded SRAMs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {10},
pages = {1127--1135},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.859480},
doi = {10.1109/TVLSI.2005.859480},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangMPCD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WangTC05,
author = {Chua{-}Chin Wang and
Yih{-}Long Tseng and
Chih{-}Chiang Chiu},
title = {A temperature-insensitive self-recharging circuitry used in DRAMs},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {3},
pages = {405--408},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.842878},
doi = {10.1109/TVLSI.2004.842878},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WangTC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WormITM05,
author = {Frederic Worm and
Paolo Ienne and
Patrick Thiran and
Giovanni De Micheli},
title = {A robust self-calibrating transmission scheme for on-chip networks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {1},
pages = {126--139},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.834241},
doi = {10.1109/TVLSI.2004.834241},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WormITM05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/WuSWHC05,
author = {Chien{-}Ming Wu and
Ming{-}Der Shieh and
Chien{-}Hsing Wu and
Yin{-}Tsung Hwang and
Jun{-}Hong Chen},
title = {{VLSI} architectural design tradeoffs for sliding-window log-MAP decoders},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {4},
pages = {439--447},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.842917},
doi = {10.1109/TVLSI.2004.842917},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/WuSWHC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XiongH05,
author = {Jinjun Xiong and
Lei He},
title = {Extended global routing with {RLC} crosstalk constraints},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {3},
pages = {319--329},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.842896},
doi = {10.1109/TVLSI.2004.842896},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/XiongH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XiuY05,
author = {Liming Xiu and
Zhihong You},
title = {A "Flying-Adder" frequency synthesis architecture of reducing {VCO}
stages},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {2},
pages = {201--210},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.840776},
doi = {10.1109/TVLSI.2004.840776},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/XiuY05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XuN05,
author = {Qiang Xu and
Nicola Nicolici},
title = {Wrapper design for multifrequency {IP} cores},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {6},
pages = {678--685},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.848811},
doi = {10.1109/TVLSI.2005.848811},
timestamp = {Thu, 30 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/XuN05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/XuN05a,
author = {Qiang Xu and
Nicola Nicolici},
title = {Modular and rapid testing of SOCs with unwrapped logic blocks},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {11},
pages = {1275--1285},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.859585},
doi = {10.1109/TVLSI.2005.859585},
timestamp = {Thu, 30 Mar 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/XuN05a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YangJBKKK05,
author = {Ge Yang and
Seong{-}Ook Jung and
Kwang{-}Hyun Baek and
Soo Hwan Kim and
Suki Kim and
Sung{-}Mo Kang},
title = {A 32-bit carry lookahead adder using dual-path all-N logic},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {8},
pages = {992--996},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.853605},
doi = {10.1109/TVLSI.2005.853605},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YangJBKKK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YoussefAE05,
author = {Ahmed Youssef and
Mohab Anis and
Mohamed I. Elmasry},
title = {{POMR:} a power-aware interconnect optimization methodology},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {3},
pages = {297--307},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.842901},
doi = {10.1109/TVLSI.2004.842901},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/YoussefAE05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/YuDJMY05,
author = {Xiaopeng Yu and
Manh Anh Do and
Lin Jia and
Jianguo Ma and
Kiat Seng Yeo},
title = {Design of a low power wide-band high resolution programmable frequency
divider},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {9},
pages = {1098--1103},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.857153},
doi = {10.1109/TVLSI.2005.857153},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/YuDJMY05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhaiBSF05,
author = {Bo Zhai and
David T. Blaauw and
Dennis Sylvester and
Kriszti{\'{a}}n Flautner},
title = {The limit of dynamic voltage scaling and insomniac dynamic voltage
scaling},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {11},
pages = {1239--1252},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.859588},
doi = {10.1109/TVLSI.2005.859588},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhaiBSF05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangP05,
author = {Xinmiao Zhang and
Keshab K. Parhi},
title = {Fast factorization architecture in soft-decision Reed-Solomon decoding},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
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pages = {413--426},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2004.842914},
doi = {10.1109/TVLSI.2004.842914},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangP05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ZhangP05a,
author = {Xinmiao Zhang and
Keshab K. Parhi},
title = {High-Speed Architectures for Parallel Long {BCH} Encoders},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {13},
number = {7},
pages = {872--877},
year = {2005},
url = {https://doi.org/10.1109/TVLSI.2005.850125},
doi = {10.1109/TVLSI.2005.850125},
timestamp = {Wed, 11 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tvlsi/ZhangP05a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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