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@inproceedings{DBLP:conf/date/MoreiraYCCZKQKK20,
author = {Orlando Moreira and
Amirreza Yousefzadeh and
Fabian Chersi and
Gokturk Cinserin and
Rik{-}Jan Zwartenkot and
Ajay Kapoor and
Peng Qiao and
Peter Kievits and
Mina A. Khoei and
Louis Rouillard and
Aimee Ferouge and
Jonathan Tapson and
Ashoka Visweswara},
title = {NeuronFlow: a neuromorphic processor architecture for Live {AI} applications},
booktitle = {2020 Design, Automation {\&} Test in Europe Conference {\&}
Exhibition, {DATE} 2020, Grenoble, France, March 9-13, 2020},
pages = {840--845},
publisher = {{IEEE}},
year = {2020},
url = {https://doi.org/10.23919/DATE48585.2020.9116352},
doi = {10.23919/DATE48585.2020.9116352},
timestamp = {Thu, 25 Jun 2020 12:55:44 +0200},
biburl = {https://dblp.org/rec/conf/date/MoreiraYCCZKQKK20.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/mj/KakoeeSPB12,
author = {Mohammad Reza Kakoee and
Ashoka Visweswara Sathanur and
Antonio Pullini and
Luca Benini},
title = {Row-based {FBB:} {A} design-time optimization for post-silicon tunable
circuits},
journal = {Microelectron. J.},
volume = {43},
number = {7},
pages = {456--465},
year = {2012},
url = {https://doi.org/10.1016/j.mejo.2012.04.001},
doi = {10.1016/J.MEJO.2012.04.001},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/mj/KakoeeSPB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SathanurBMMP11,
author = {Ashoka Visweswara Sathanur and
Luca Benini and
Alberto Macii and
Enrico Macii and
Massimo Poncino},
title = {Fast Computation of Discharge Current Upper Bounds for Clustered Power
Gating},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {19},
number = {1},
pages = {146--151},
year = {2011},
url = {https://doi.org/10.1109/TVLSI.2009.2029276},
doi = {10.1109/TVLSI.2009.2029276},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SathanurBMMP11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/SathanurBMMP11a,
author = {Ashoka Visweswara Sathanur and
Luca Benini and
Alberto Macii and
Enrico Macii and
Massimo Poncino},
title = {Row-Based Power-Gating: {A} Novel Sleep Transistor Insertion Methodology
for Leakage Power Optimization in Nanometer {CMOS} Circuits},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {19},
number = {3},
pages = {469--482},
year = {2011},
url = {https://doi.org/10.1109/TVLSI.2009.2035448},
doi = {10.1109/TVLSI.2009.2035448},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/SathanurBMMP11a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ArtesASHC11,
author = {Antonio Art{\'{e}}s and
Jos{\'{e}} Luis Ayala and
Ashoka Visweswara Sathanur and
Jos Huisken and
Francky Catthoor},
title = {Run-time self-tuning banked loop buffer architecture for power optimization
of dynamic workload applications},
booktitle = {{IEEE/IFIP} 19th International Conference on {VLSI} and System-on-Chip,
VLSI-SoC 2011, Kowloon, Hong Kong, China, October 3-5, 2011},
pages = {136--141},
publisher = {{IEEE}},
year = {2011},
url = {https://doi.org/10.1109/VLSISoC.2011.6081635},
doi = {10.1109/VLSISOC.2011.6081635},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/ArtesASHC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/icecsys/SathanurHSG10,
author = {Ashoka Visweswara Sathanur and
Jos Huisken and
Jan Stuyt and
Harmke de Groot},
title = {Activity profile driven simultaneous vt assignment and power switch
sizing for leakage power minimization in nanometer {CMOS} designs},
booktitle = {17th {IEEE} International Conference on Electronics, Circuits, and
Systems, {ICECS} 2010, Athens, Greece, 12-15 December, 2010},
pages = {519--522},
publisher = {{IEEE}},
year = {2010},
url = {https://doi.org/10.1109/ICECS.2010.5724563},
doi = {10.1109/ICECS.2010.5724563},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/icecsys/SathanurHSG10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/KakoeeSPHB10,
author = {Mohammad Reza Kakoee and
Ashoka Visweswara Sathanur and
Antonio Pullini and
Jos Huisken and
Luca Benini},
editor = {Vojin G. Oklobdzija and
Barry Pangle and
Naehyuck Chang and
Naresh R. Shanbhag and
Chris H. Kim},
title = {Automatic synthesis of near-threshold circuits with fine-grained performance
tunability},
booktitle = {Proceedings of the 2010 International Symposium on Low Power Electronics
and Design, 2010, Austin, Texas, USA, August 18-20, 2010},
pages = {401--406},
publisher = {{ACM}},
year = {2010},
url = {https://doi.org/10.1145/1840845.1840934},
doi = {10.1145/1840845.1840934},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/islped/KakoeeSPHB10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jolpe/SathanurBMMP09,
author = {Ashoka Visweswara Sathanur and
Luca Benini and
Alberto Macii and
Enrico Macii and
Massimo Poncino},
title = {Exploiting Temporal Discharge Current Information to Improve the Efficiency
of Clustered Power-Gating},
journal = {J. Low Power Electron.},
volume = {5},
number = {1},
pages = {113--121},
year = {2009},
url = {https://doi.org/10.1166/jolpe.2009.1004},
doi = {10.1166/JOLPE.2009.1004},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/jolpe/SathanurBMMP09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/SathanurPBMM09,
author = {Ashoka Visweswara Sathanur and
Antonio Pullini and
Luca Benini and
Giovanni De Micheli and
Enrico Macii},
editor = {Luca Benini and
Giovanni De Micheli and
Bashir M. Al{-}Hashimi and
Wolfgang M{\"{u}}ller},
title = {Physically clustered forward body biasing for variability compensation
in nanometer {CMOS} design},
booktitle = {Design, Automation and Test in Europe, {DATE} 2009, Nice, France,
April 20-24, 2009},
pages = {154--159},
publisher = {{IEEE}},
year = {2009},
url = {https://doi.org/10.1109/DATE.2009.5090650},
doi = {10.1109/DATE.2009.5090650},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/SathanurPBMM09.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/integration/ChakrabortyDSSMMP08,
author = {Ashutosh Chakraborty and
Karthik Duraisami and
Ashoka Visweswara Sathanur and
Prassanna Sithambaram and
Alberto Macii and
Enrico Macii and
Massimo Poncino},
title = {Implementation of a thermal management unit for canceling temperature-dependent
clock skew variations},
journal = {Integr.},
volume = {41},
number = {1},
pages = {2--8},
year = {2008},
url = {https://doi.org/10.1016/j.vlsi.2007.03.002},
doi = {10.1016/J.VLSI.2007.03.002},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/integration/ChakrabortyDSSMMP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/jolpe/CalimeraDSSBMMP08,
author = {Andrea Calimera and
Karthik Duraisami and
Ashoka Visweswara Sathanur and
Prassanna Sithambaram and
R. Iris Bahar and
Alberto Macii and
Enrico Macii and
Massimo Poncino},
title = {Thermal-Aware Design Techniques for Nanometer {CMOS} Circuits},
journal = {J. Low Power Electron.},
volume = {4},
number = {3},
pages = {374--384},
year = {2008},
url = {https://doi.org/10.1166/jolpe.2008.190},
doi = {10.1166/JOLPE.2008.190},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/jolpe/CalimeraDSSBMMP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tvlsi/ChakrabortyDSSBMMP08,
author = {Ashutosh Chakraborty and
Karthik Duraisami and
Ashoka Visweswara Sathanur and
Prassanna Sithambaram and
Luca Benini and
Alberto Macii and
Enrico Macii and
Massimo Poncino},
title = {Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers},
journal = {{IEEE} Trans. Very Large Scale Integr. Syst.},
volume = {16},
number = {6},
pages = {639--649},
year = {2008},
url = {https://doi.org/10.1109/TVLSI.2008.2000248},
doi = {10.1109/TVLSI.2008.2000248},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tvlsi/ChakrabortyDSSBMMP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/SathanurPBMMP08,
author = {Ashoka Visweswara Sathanur and
Antonio Pullini and
Luca Benini and
Alberto Macii and
Enrico Macii and
Massimo Poncino},
editor = {Donatella Sciuto},
title = {A Scalable Algorithmic Framework for Row-Based Power-Gating},
booktitle = {Design, Automation and Test in Europe, {DATE} 2008, Munich, Germany,
March 10-14, 2008},
pages = {379--384},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1109/DATE.2008.4484710},
doi = {10.1109/DATE.2008.4484710},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/date/SathanurPBMMP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/SathanurPBMMP08,
author = {Ashoka Visweswara Sathanur and
Antonio Pullini and
Luca Benini and
Alberto Macii and
Enrico Macii and
Massimo Poncino},
editor = {Vijaykrishnan Narayanan and
Zhiyuan Yan and
Enrico Macii and
Sanjukta Bhanja},
title = {Optimal sleep transistor synthesis under timing and area constraints},
booktitle = {Proceedings of the 18th {ACM} Great Lakes Symposium on {VLSI} 2008,
Orlando, Florida, USA, May 4-6, 2008},
pages = {177--182},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1366110.1366155},
doi = {10.1145/1366110.1366155},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/SathanurPBMMP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/SathanurCPBMMP08,
author = {Ashoka Visweswara Sathanur and
Andrea Calimera and
Antonio Pullini and
Luca Benini and
Alberto Macii and
Enrico Macii and
Massimo Poncino},
title = {On quantifying the figures of merit of power-gating for leakage power
minimization in nanometer {CMOS} circuits},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2008), 18-21
May 2008, Sheraton Seattle Hotel, Seattle, Washington, {USA}},
pages = {2761--2764},
publisher = {{IEEE}},
year = {2008},
url = {https://doi.org/10.1109/ISCAS.2008.4542029},
doi = {10.1109/ISCAS.2008.4542029},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/SathanurCPBMMP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/SathanurBMMP08,
author = {Ashoka Visweswara Sathanur and
Luca Benini and
Alberto Macii and
Enrico Macii and
Massimo Poncino},
editor = {Vijaykrishnan Narayanan and
C. P. Ravikumar and
J{\"{o}}rg Henkel and
Ali Keshavarzi and
Vojin G. Oklobdzija and
Barry M. Pangrle},
title = {Multiple power-gating domain (multi-VGND) architecture for improved
leakage power reduction},
booktitle = {Proceedings of the 2008 International Symposium on Low Power Electronics
and Design, 2008, Bangalore, India, August 11-13, 2008},
pages = {51--56},
publisher = {{ACM}},
year = {2008},
url = {https://doi.org/10.1145/1393921.1393938},
doi = {10.1145/1393921.1393938},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/islped/SathanurBMMP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/SathanurBMMP08,
author = {Ashoka Visweswara Sathanur and
Luca Benini and
Alberto Macii and
Enrico Macii and
Massimo Poncino},
editor = {Lars Svensson and
Jos{\'{e}} Monteiro},
title = {Temporal Discharge Current Driven Clustering for Improved Leakage
Power Reduction in Row-Based Power-Gating},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 18th International Workshop, {PATMOS} 2008, Lisbon,
Portugal, September 10-12, 2008. Revised Selected Papers},
series = {Lecture Notes in Computer Science},
volume = {5349},
pages = {42--51},
publisher = {Springer},
year = {2008},
url = {https://doi.org/10.1007/978-3-540-95948-9\_5},
doi = {10.1007/978-3-540-95948-9\_5},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/SathanurBMMP08.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/date/SathanurCBMMP07,
author = {Ashoka Visweswara Sathanur and
Andrea Calimera and
Luca Benini and
Alberto Macii and
Enrico Macii and
Massimo Poncino},
editor = {Rudy Lauwereins and
Jan Madsen},
title = {Interactive presentation: Efficient computation of discharge current
upper bounds for clustered sleep transistor sizing},
booktitle = {2007 Design, Automation and Test in Europe Conference and Exposition,
{DATE} 2007, Nice, France, April 16-20, 2007},
pages = {1544--1549},
publisher = {{EDA} Consortium, San Jose, CA, {USA}},
year = {2007},
url = {https://dl.acm.org/citation.cfm?id=1266704},
timestamp = {Wed, 16 Oct 2019 14:14:53 +0200},
biburl = {https://dblp.org/rec/conf/date/SathanurCBMMP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/glvlsi/CalimeraPSBMMP07,
author = {Andrea Calimera and
Antonio Pullini and
Ashoka Visweswara Sathanur and
Luca Benini and
Alberto Macii and
Enrico Macii and
Massimo Poncino},
editor = {Hai Zhou and
Enrico Macii and
Zhiyuan Yan and
Yehia Massoud},
title = {Design of a family of sleep transistor cells for a clustered power-gating
flow in 65nm technology},
booktitle = {Proceedings of the 17th {ACM} Great Lakes Symposium on {VLSI} 2007,
Stresa, Lago Maggiore, Italy, March 11-13, 2007},
pages = {501--504},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1228784.1228903},
doi = {10.1145/1228784.1228903},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/glvlsi/CalimeraPSBMMP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/DuraisamiSSMMP07,
author = {Karthik Duraisami and
Prassanna Sithambaram and
Ashoka Visweswara Sathanur and
Alberto Macii and
Enrico Macii and
Massimo Poncino},
title = {Design Exploration of a Thermal Management Unit for Dynamic Control
of Temperature-Induced Clock Skew},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2007), 27-20
May 2007, New Orleans, Louisiana, {USA}},
pages = {1061--1064},
publisher = {{IEEE}},
year = {2007},
url = {https://doi.org/10.1109/ISCAS.2007.378192},
doi = {10.1109/ISCAS.2007.378192},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/DuraisamiSSMMP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/SathanurPBMMP07,
author = {Ashoka Visweswara Sathanur and
Antonio Pullini and
Luca Benini and
Alberto Macii and
Enrico Macii and
Massimo Poncino},
editor = {Diana Marculescu and
Anand Raghunathan and
Ali Keshavarzi and
Vijaykrishnan Narayanan},
title = {Timing-driven row-based power gating},
booktitle = {Proceedings of the 2007 International Symposium on Low Power Electronics
and Design, 2007, Portland, OR, USA, August 27-29, 2007},
pages = {104--109},
publisher = {{ACM}},
year = {2007},
url = {https://doi.org/10.1145/1283780.1283803},
doi = {10.1145/1283780.1283803},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/islped/SathanurPBMMP07.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/iscas/ChakrabortyDSSMMP06,
author = {Ashutosh Chakraborty and
Karthik Duraisami and
Ashoka Visweswara Sathanur and
Prassanna Sithambaram and
Alberto Macii and
Enrico Macii and
Massimo Poncino},
title = {Implications of ultra low-voltage devices on design techniques for
controlling leakage in NanoCMOS circuits},
booktitle = {International Symposium on Circuits and Systems {(ISCAS} 2006), 21-24
May 2006, Island of Kos, Greece},
publisher = {{IEEE}},
year = {2006},
url = {https://doi.org/10.1109/ISCAS.2006.1692515},
doi = {10.1109/ISCAS.2006.1692515},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/iscas/ChakrabortyDSSMMP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/islped/ChakrabortyDSSBMMP06,
author = {Ashutosh Chakraborty and
Karthik Duraisami and
Ashoka Visweswara Sathanur and
Prassanna Sithambaram and
Luca Benini and
Alberto Macii and
Enrico Macii and
Massimo Poncino},
editor = {Wolfgang Nebel and
Mircea R. Stan and
Anand Raghunathan and
J{\"{o}}rg Henkel and
Diana Marculescu},
title = {Dynamic thermal clock skew compensation using tunable delay buffers},
booktitle = {Proceedings of the 2006 International Symposium on Low Power Electronics
and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006},
pages = {162--167},
publisher = {{ACM}},
year = {2006},
url = {https://doi.org/10.1145/1165573.1165612},
doi = {10.1145/1165573.1165612},
timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/islped/ChakrabortyDSSBMMP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/patmos/ChakrabortyDSSMMP06,
author = {Ashutosh Chakraborty and
Karthik Duraisami and
Ashoka Visweswara Sathanur and
Prassanna Sithambaram and
Alberto Macii and
Enrico Macii and
Massimo Poncino},
editor = {Johan Vounckx and
Nadine Az{\'{e}}mard and
Philippe Maurine},
title = {Dynamic Management of Thermally-Induced Clock Skew: An Implementation
Perspective},
booktitle = {Integrated Circuit and System Design. Power and Timing Modeling, Optimization
and Simulation, 16th International Workshop, {PATMOS} 2006, Montpellier,
France, September 13-15, 2006, Proceedings},
series = {Lecture Notes in Computer Science},
volume = {4148},
pages = {214--224},
publisher = {Springer},
year = {2006},
url = {https://doi.org/10.1007/11847083\_21},
doi = {10.1007/11847083\_21},
timestamp = {Sat, 30 Sep 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/patmos/ChakrabortyDSSMMP06.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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