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@proceedings{DBLP:conf/vlsi/1993,
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
publisher = {North-Holland},
year = {1994},
isbn = {0-444-89911-1},
timestamp = {Thu, 03 Jan 2002 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/1993.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BoldingCCEHNW93,
author = {Kevin Bolding and
Sen{-}Ching S. Cheung and
Sung{-}Eun Choi and
Carl Ebeling and
Soha Hassoun and
Ton Anh Ngo and
Robert Wille},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {The chaos router chip: design and implementation of an adaptive router},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {311--320},
publisher = {North-Holland},
year = {1993},
timestamp = {Fri, 15 Nov 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/BoldingCCEHNW93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BorelMM93,
author = {Joseph Borel and
J. Monnier and
G{\'{e}}rard Matheron},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {The single chip system era},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {3--12},
publisher = {North-Holland},
year = {1993},
timestamp = {Fri, 29 May 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/BorelMM93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/BrasenG93,
author = {Daniel R. Brasen and
Arnold Ginetti},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {Post-placement technology mapping},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {15--24},
publisher = {North-Holland},
year = {1993},
timestamp = {Thu, 03 Jan 2002 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/BrasenG93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/CabonDC93,
author = {Bertrand Cabon and
T. V. Dinh and
J. Chilo},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {Superconductive interconnections in multi-chip modules},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {291--298},
publisher = {North-Holland},
year = {1993},
timestamp = {Thu, 03 Jan 2002 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/CabonDC93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ChangG93,
author = {J. Morris Chang and
Edward F. Gehringer},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {Performance of object caching for object-oriented systems},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {83--91},
publisher = {North-Holland},
year = {1993},
timestamp = {Thu, 03 Jan 2002 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ChangG93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ErbarKH93,
author = {Maximilian Erbar and
Ingo K{\"{o}}nenkamp and
Ernst{-}Helmut Horneber},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {Solving the partial differential equations of transmission lines with
wave digital filters},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {241--250},
publisher = {North-Holland},
year = {1993},
timestamp = {Thu, 03 Jan 2002 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ErbarKH93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/FurberDGPW93,
author = {Stephen B. Furber and
Paul Day and
Jim D. Garside and
N. C. Paver and
John V. Woods},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {A micropipelined {ARM}},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {211--220},
publisher = {North-Holland},
year = {1993},
timestamp = {Wed, 12 Jun 2013 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/FurberDGPW93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GopalakrishnanA93,
author = {Ganesh Gopalakrishnan and
Venkatesh Akella},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {A transformational approach to asynchronous high-level synthesis},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {201--210},
publisher = {North-Holland},
year = {1993},
timestamp = {Thu, 03 Jan 2002 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/GopalakrishnanA93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/GosselS93,
author = {Michael G{\"{o}}ssel and
Egor S. Sogomonyan},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {Self-parity cominational circuits for self-testing, concurrent fault
detection and parity scan design},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {103--111},
publisher = {North-Holland},
year = {1993},
timestamp = {Tue, 22 Oct 2002 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/GosselS93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/HabigerJ93,
author = {Claus M. Habiger and
Ian P. Jalowiecki},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {The implementation of a {MCM} associative string processor},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {283--289},
publisher = {North-Holland},
year = {1993},
timestamp = {Thu, 03 Jan 2002 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/HabigerJ93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Hauser93,
author = {Hermann Hauser},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {Personal Communicators: {A} better way to stay in touch},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {57--61},
publisher = {North-Holland},
year = {1993},
timestamp = {Thu, 03 Jan 2002 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/Hauser93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/JacquetS93,
author = {D. Jacquet and
Gabriele Saucier},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {Design of a dedicated neural network on silicon: application to optical
character recognition},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {169--178},
publisher = {North-Holland},
year = {1993},
timestamp = {Thu, 03 Jan 2002 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/JacquetS93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Jensen93,
author = {Poul Martin Rands Jensen},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {An {ASIC} array architecture for the {DITPOS} algorithm},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {73--82},
publisher = {North-Holland},
year = {1993},
timestamp = {Thu, 03 Jan 2002 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/Jensen93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LadageL93,
author = {Lorenz Ladage and
Georg Lodde},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {A 45{\textdegree} compaction algorithm handling overconstraints},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {45--54},
publisher = {North-Holland},
year = {1993},
timestamp = {Thu, 03 Jan 2002 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/LadageL93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Leveugle93,
author = {R{\'{e}}gis Leveugle},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {Test of single fault tolerant controllers in {VLSI} circuits},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {123--132},
publisher = {North-Holland},
year = {1993},
timestamp = {Mon, 03 Feb 2003 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/Leveugle93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/LinK93,
author = {Shen Lin and
Ernest S. Kuh},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {Circuit simulation for large interconnected {IC} networks},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {333--342},
publisher = {North-Holland},
year = {1993},
timestamp = {Tue, 27 Mar 2018 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/LinK93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/MoussaSG93,
author = {Imed Moussa and
Ali Skaf and
Alain Guyot},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {Design of a GaAs redundant divider},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {63--72},
publisher = {North-Holland},
year = {1993},
timestamp = {Thu, 03 Jan 2002 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/MoussaSG93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Muller93,
author = {Mike Muller},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {{ARM6:} Processor design for high performance at low power},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {181--189},
publisher = {North-Holland},
year = {1993},
timestamp = {Thu, 03 Jan 2002 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/Muller93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Muller93a,
author = {Markus M{\"{u}}ller},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {Bondgraph execution as a new algorithm for circuit simulation},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {343--352},
publisher = {North-Holland},
year = {1993},
timestamp = {Mon, 27 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/Muller93a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/NguyenL93,
author = {Kim{-}Minh Nguyen and
Martin C. Lefebvre},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {A family of module generators for the layout synthesis of {I/O} buffers},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {35--44},
publisher = {North-Holland},
year = {1993},
timestamp = {Thu, 03 Jan 2002 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/NguyenL93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PalaniswamyW93,
author = {Avinash C. Palaniswamy and
Philip A. Wilsey},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {Adaptive checkpoint intervals in an optimistically synchronised parallel
digital system simulator},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {353--362},
publisher = {North-Holland},
year = {1993},
timestamp = {Thu, 03 Jan 2002 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/PalaniswamyW93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/PoirierHBJ93,
author = {F. Poirier and
Jean{-}Claude Heudin and
M. Belleville and
C. Jaffard},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {A high performance {RISC} microprocessor},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {221--228},
publisher = {North-Holland},
year = {1993},
timestamp = {Thu, 03 Jan 2002 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/PoirierHBJ93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Poussart93,
author = {D. Poussart},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {Opportunities for integrating early-vision computation algorithms
and {VLSI} technology to the development of smart sensors},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {145--150},
publisher = {North-Holland},
year = {1993},
timestamp = {Thu, 03 Jan 2002 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/Poussart93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/RothigMD93,
author = {Wolfgang R{\"{o}}thig and
Elmar U. K. Melcher and
Michel Dana},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {Probabilistic power consumption estimation in digital circuits},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {231--240},
publisher = {North-Holland},
year = {1993},
timestamp = {Thu, 24 May 2007 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/RothigMD93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SchneiderWZ93,
author = {M. Schneider and
Utz Wever and
Qinghua Zheng},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {Parallel harmonic balance},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {251--260},
publisher = {North-Holland},
year = {1993},
timestamp = {Thu, 03 Jan 2002 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SchneiderWZ93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SchonfeldP93,
author = {J{\"{o}}rg Sch{\"{o}}nfeld and
Peter Pirsch},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {Single board image processing unit for vehicle guidance},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {151--160},
publisher = {North-Holland},
year = {1993},
timestamp = {Mon, 17 Dec 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SchonfeldP93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/ShigehiroNSK93,
author = {Yuji Shigehiro and
Takashi Nagata and
Isao Shirakawa and
Takashi Kambe},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {Optimal layout recycling based on graph theoretic linear programming
approach},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {25--34},
publisher = {North-Holland},
year = {1993},
timestamp = {Thu, 03 Jan 2002 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/ShigehiroNSK93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SkafBGM93,
author = {Ali Skaf and
Jean{-}Claude Bajard and
Alain Guyot and
Jean{-}Michel Muller},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {A {VLSI} circuit for on-line polynominal computing: Application to
exponential, trigonometric and hyperbolic functions},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {93--100},
publisher = {North-Holland},
year = {1993},
timestamp = {Thu, 03 Jan 2002 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SkafBGM93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SmitBS93,
author = {Jaap Smit and
Mark J. Bentum and
Martin M. Samsom},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {Implementation of the volume rendering algorithm using a low-power
design-style},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {161--168},
publisher = {North-Holland},
year = {1993},
timestamp = {Thu, 07 Aug 2008 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/SmitBS93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/Stroele93,
author = {Albrecht P. Stroele},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {Partitioning and hierarchical description of self-testable designs},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {113--122},
publisher = {North-Holland},
year = {1993},
timestamp = {Thu, 03 Jan 2002 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/Stroele93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/SvenssonY93,
author = {Christer Svensson and
Jiren Yuan},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {Ultra high speed {CMOS} design},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {273--282},
publisher = {North-Holland},
year = {1993},
timestamp = {Thu, 03 Jan 2002 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/SvenssonY93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/TanakaI93,
author = {Mikiko Sode Tanaka and
Masaki Ishikawa},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {A multilayer channel router based on optimal multilayer net assignment},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {301--310},
publisher = {North-Holland},
year = {1993},
timestamp = {Thu, 03 Jan 2002 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/TanakaI93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/WallerA93,
author = {W. A. J. Waller and
S. M. Aziz},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {A C-testable parallel multiplier using differential cascode voltage
switch {(DDVS)} logic},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {133--142},
publisher = {North-Holland},
year = {1993},
timestamp = {Thu, 03 Jan 2002 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/WallerA93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/WehnGV93,
author = {Norbert Wehn and
Manfred Glesner and
C. Vielhauer},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {Estimating lower hardware bounds in high-level synthesis},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {261--270},
publisher = {North-Holland},
year = {1993},
timestamp = {Thu, 03 Jan 2002 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/WehnGV93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/WerfAHMVL93,
author = {Albert van der Werf and
Emile H. L. Aarts and
E. W. Heijnen and
Jef L. van Meerbergen and
Wim F. J. Verhaegh and
Paul E. R. Lippens},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {A new method for retiming multi-functional processing units},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {191--200},
publisher = {North-Holland},
year = {1993},
timestamp = {Mon, 23 Jun 2003 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/vlsi/WerfAHMVL93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/vlsi/XueFK93,
author = {Tianxiong Xue and
Takashi Fujii and
Ernest S. Kuh},
editor = {Kakayuki Yanagawa and
Peter A. Ivey},
title = {A new performance-driven global routing algorithm for gate array},
booktitle = {{VLSI} 93, Proceedings of the {IFIP} {TC10/WG} 10.5 International
Conference on Very Large Scale Integration, Grenoble, France, 7-10
September, 1993},
series = {{IFIP} Transactions},
volume = {{A-42}},
pages = {321--330},
publisher = {North-Holland},
year = {1993},
timestamp = {Thu, 03 Jan 2002 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/vlsi/XueFK93.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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