Stop the war!
Остановите войну!
for scientists:
default search action
Search dblp for Publications
export results for "toc:db/journals/integration/integration29.bht:"
@article{DBLP:journals/integration/BeeftinkKKPS00, author = {Frederik Beeftink and Prabhakar Kudva and David S. Kung and Ruchir Puri and Leon Stok}, title = {Combinatorial cell design for {CMOS} libraries}, journal = {Integr.}, volume = {29}, number = {1}, pages = {67--93}, year = {2000}, url = {https://doi.org/10.1016/S0167-9260(99)00024-3}, doi = {10.1016/S0167-9260(99)00024-3}, timestamp = {Thu, 20 Feb 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/integration/BeeftinkKKPS00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/integration/BrachtendorfL00, author = {Hans Georg Brachtendorf and Rainer Laur}, title = {An accurate model for the transient simulation of lossy interconnects based on a novel discretization formula}, journal = {Integr.}, volume = {29}, number = {2}, pages = {117--129}, year = {2000}, url = {https://doi.org/10.1016/S0167-9260(00)00004-3}, doi = {10.1016/S0167-9260(00)00004-3}, timestamp = {Thu, 20 Feb 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/integration/BrachtendorfL00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/integration/EvenMS00, author = {Guy Even and Silvia M. M{\"{u}}ller and Peter{-}Michael Seidel}, title = {A dual precision {IEEE} floating-point multiplier}, journal = {Integr.}, volume = {29}, number = {2}, pages = {167--180}, year = {2000}, url = {https://doi.org/10.1016/S0167-9260(00)00006-7}, doi = {10.1016/S0167-9260(00)00006-7}, timestamp = {Thu, 20 Feb 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/integration/EvenMS00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/integration/JongeneelO00, author = {Dirk{-}Jan Jongeneel and Ralph H. J. M. Otten}, title = {Technology mapping for area and speed}, journal = {Integr.}, volume = {29}, number = {1}, pages = {45--66}, year = {2000}, url = {https://doi.org/10.1016/S0167-9260(99)00023-1}, doi = {10.1016/S0167-9260(99)00023-1}, timestamp = {Thu, 20 Feb 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/integration/JongeneelO00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/integration/OttenB00, author = {Ralph H. J. M. Otten and Robert K. Brayton}, title = {Performance planning}, journal = {Integr.}, volume = {29}, number = {1}, pages = {1--24}, year = {2000}, url = {https://doi.org/10.1016/S0167-9260(99)00022-X}, doi = {10.1016/S0167-9260(99)00022-X}, timestamp = {Thu, 20 Feb 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/integration/OttenB00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/integration/SouaniATT00, author = {Chokri Souani and Mohamed Abid and Kholdoun Torki and Rached Tourki}, title = {{VLSI} design of 1-D {DWT} architecture with parallel filters}, journal = {Integr.}, volume = {29}, number = {2}, pages = {181--207}, year = {2000}, url = {https://doi.org/10.1016/S0167-9260(00)00007-9}, doi = {10.1016/S0167-9260(00)00007-9}, timestamp = {Thu, 20 Feb 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/integration/SouaniATT00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/integration/TabbaraTBN00, author = {Abdallah Tabbara and Bassam Tabbara and Robert K. Brayton and A. Richard Newton}, title = {Integration of retiming with architectural floorplanning}, journal = {Integr.}, volume = {29}, number = {1}, pages = {25--43}, year = {2000}, url = {https://doi.org/10.1016/S0167-9260(99)00021-8}, doi = {10.1016/S0167-9260(99)00021-8}, timestamp = {Thu, 20 Feb 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/integration/TabbaraTBN00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/integration/TangF00, author = {Kevin T. Tang and Eby G. Friedman}, title = {Delay and noise estimation of {CMOS} logic gates driving coupled resistive-capacitive interconnections}, journal = {Integr.}, volume = {29}, number = {2}, pages = {131--165}, year = {2000}, url = {https://doi.org/10.1016/S0167-9260(00)00005-5}, doi = {10.1016/S0167-9260(00)00005-5}, timestamp = {Thu, 20 Feb 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/integration/TangF00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
@article{DBLP:journals/integration/ZuzekDT00, author = {A. Zuzek and Rolf Drechsler and Mitchell A. Thornton}, title = {Boolean function representation and spectral characterization using {AND/OR} graphs}, journal = {Integr.}, volume = {29}, number = {2}, pages = {101--116}, year = {2000}, url = {https://doi.org/10.1016/S0167-9260(00)00003-1}, doi = {10.1016/S0167-9260(00)00003-1}, timestamp = {Thu, 20 Feb 2020 00:00:00 +0100}, biburl = {https://dblp.org/rec/journals/integration/ZuzekDT00.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.