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Publication search results
found 68 matches
- 2023
- Ali Khakpour, Ghader Karimian:
An Oversampling-Based Fast Convergent Blind Technique for Gain Mismatch and Timing Skew Error Correction in Time-Interleaved ADCs. Circuits Syst. Signal Process. 42(4): 2416-2432 (2023) - Kangning Wang, Huidong Zhao, Jiliang Liu, Jialu Yin, Zhi Li, Shushan Qiao:
A low-overhead in-situ timing-error prediction technique with wide-voltage-range transition-detector for variation-tolerant digital circuits. IEICE Electron. Express 20(11): 20230145 (2023) - Zhengguo Shen, Weiwei Shan, Yuxuan Du, Ziyu Li, Jun Yang:
Beyond Eliminating Timing Margin: An Efficient and Reliable Negative Margin Timing Error Detection for Neural Network Accelerator Without Accuracy Loss. IEEE J. Solid State Circuits 58(5): 1462-1471 (2023) - Ahmed Abdelaziz, Mohamed Ahmed, Tawfiq Musah:
Hybrid Timing Error Detector for Baud Rate Multilevel Clock and Data Recovery. IEEE Open J. Circuits Syst. 4: 324-335 (2023) - Zuodong Zhang, Zizheng Guo, Yibo Lin, Meng Li, Runsheng Wang, Ru Huang:
AVATAR: An Aging- and Variation-Aware Dynamic Timing Analyzer for Error-Efficient Computing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(11): 4139-4151 (2023) - Hao Zhang, Weifeng He, Yanan Sun, Mingoo Seok:
A DFT-Compatible In-Situ Timing Error Detection and Correction Structure Featuring Low Area and Test Overhead. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(3): 1015-1028 (2023) - 2022
- Abhishek Jain, Andrea Mario Veggetti, Dennis Crippa, Antonio Benfante, Simone Gerardin, Marta Bagatin:
Radiation Tolerant Multi-Bit Flip-Flop System With Embedded Timing Pre-Error Sensing. IEEE J. Solid State Circuits 57(9): 2878-2890 (2022) - Yizhak Shifman, Inbal Stanger, Netanel Shavit, Ramiro Taco, Alexander Fish, Joseph Shor:
A Method for Mitigation of Droop Timing Errors Including a 500 MHz Droop Detector and Dual Mode Logic. IEEE J. Solid State Circuits 57(2): 596-608 (2022) - Tawfiq Musah, Abishek Namachivayam:
Robust Timing Error Detection for Multilevel Baud-Rate CDR. IEEE Trans. Circuits Syst. I Regul. Pap. 69(10): 3927-3939 (2022) - 2021
- Ali Khakpour, Ghader Karimian:
A New Fast Convergent Blind Timing Skew Error Correction Structure for TIADC. IEEE Trans. Circuits Syst. II Express Briefs 68(4): 1512-1516 (2021) - Isaak Yang, Kwang-Hyun Cho:
A Low-Power Timing-Error-Tolerant Circuit by Controlling a Clock. IEEE Trans. Very Large Scale Integr. Syst. 29(3): 512-518 (2021) - Stavros Simoglou, Christos P. Sotiriou, Nikolaos Blias:
Static Timing Analysis Induced Simulation Errors for Asynchronous Circuits. DFT 2021: 1-4 - Hao Zhang, Weifeng He, Yanan Sun, Mingoo Seok:
An Area-Efficient Scannable In Situ Timing Error Detection Technique Featuring Low Test Overhead for Resilient Circuits. ICCAD 2021: 1-9 - Ioannis Tsiokanos, George Papadimitriou, Dimitris Gizopoulos, Georgios Karakonstantis:
Boosting Microprocessor Efficiency: Circuit- and Workload-Aware Assessment of Timing Errors. IISWC 2021: 125-137 - 2020
- Dam Minh Tung, Nguyen Van Toan, Jeong-Gun Lee:
In-Situ Timing Error Predictor-Based Two-Cycle Adaptive Frequency Scaling System on an FPGA. J. Circuits Syst. Comput. 29(6): 2050098:1-2050098:22 (2020) - Cheng-Yao Hong, Tsung-Te Liu:
A Variation-Resilient Microprocessor With a Two-Level Timing Error Detection and Correction System in 28-nm CMOS. IEEE J. Solid State Circuits 55(8): 2285-2294 (2020) - Sarkis Azizian, Mehdi Ehsanian:
Generalized Method for Extraction of Offset, Gain, and Timing Skew Errors in Time-Interleaved ADCs. IEEE Trans. Circuits Syst. II Express Briefs 67-II(7): 1214-1218 (2020) - Xinchao Shang, Minyi Lu, Chengjun Wu, Yiming Xiang, Jiaming Xu, Weiwei Shan:
A Wide-Voltage-Range Transition-Detector With In-Situ Timing-Error Detection and Correction Based on Pulsed-Latch Design in 28 nm CMOS. IEEE Trans. Circuits Syst. 67-I(11): 3933-3943 (2020) - 2019
- Yutaka Masuda, Masanori Hashimoto:
MTTF-Aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(7): 867-877 (2019) - Jie Zhang, Hong Zhang, Bo Yang, Ruizhi Zhang:
Joint background calibration of gain and timing mismatch errors with low hardware cost for time-interleaved ADCs. IET Circuits Devices Syst. 13(2): 203-210 (2019) - Kevin E. Murray, Andrea Suardi, Vaughn Betz, George A. Constantinides:
Calculated Risks: Quantifying Timing Error Probability With Extended Static Timing Analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(4): 719-732 (2019) - Xiaowen Wang, William H. Robinson:
Error Estimation and Error Reduction With Input-Vector Profiling for Timing Speculation in Digital Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(2): 385-389 (2019) - Weiwei Shan, Xinchao Shang, Xing Wan, Hao Cai, Chuan Zhang, Jun Yang:
A Wide-Voltage-Range Half-Path Timing Error-Detection System With a 9-Transistor Transition-Detector in 40-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 66-I(6): 2288-2297 (2019) - 2018
- Prasanthi Rathnala, Tim Wilmshurst, Ahmad H. Kharaz:
Timing error detection and correction for power efficiency: an aggressive scaling approach. IET Circuits Devices Syst. 12(6): 707-712 (2018) - Xinsheng Wang, Mingyan Yu:
The Error Bound of Timing Domain in Model Order Reduction by Krylov Subspace Methods. J. Circuits Syst. Comput. 27(6): 1850093:1-1850093:19 (2018) - Hans Reyserhove, Wim Dehaene:
Margin Elimination Through Timing Error Detection in a Near-Threshold Enabled 32-bit Microcontroller in 40-nm CMOS. IEEE J. Solid State Circuits 53(7): 2101-2113 (2018) - Paul N. Whatmough, Sae Kyu Lee, David M. Brooks, Gu-Yeon Wei:
DNN Engine: A 28-nm Timing-Error Tolerant Sparse Deep Neural Network Processor for IoT Applications. IEEE J. Solid State Circuits 53(9): 2722-2731 (2018) - Weiwei Shan, Xinchao Shang, Longxing Shi, Wentao Dai, Jun Yang:
Timing Error Prediction AVFS With Detection Window Tuning for Wide-Operating-Range ICs. IEEE Trans. Circuits Syst. II Express Briefs 65-II(7): 933-937 (2018) - Wentao Dai, Peiye Liu, Weiwei Shan:
Short-path Padding Method for Timing Error Resilient Circuits based on Transmission Gates Insertion. ACM Great Lakes Symposium on VLSI 2018: 105-110 - 2017
- Ik Joon Chang, Sang Yoon Park, Jun Won Choi:
Design of Low-Power Voltage Scalable Arithmetic Units with Perfect Timing Error Cancelation. Circuits Syst. Signal Process. 36(11): 4309-4325 (2017)
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