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Publication search results
found 129 matches
- 1987
- Prathima Agrawal, William J. Dally, Ahmed K. Ezzat, W. C. Fischer, H. V. Jagadish, A. S. Krishnakumar:
Architecture and Design of the MARS Hardware Accelerator. DAC 1987: 101-107 - J. Apte, Gershon Kedem:
Strip Layout: A New Layout Methodology for Standard Circuit Modules. DAC 1987: 363-369 - Bernd Becker, Günter Hotz, Reiner Kolla, Paul Molitor, Hans-Georg Osthof:
Hierarchical Design Based on a Calculus of Nets. DAC 1987: 649-653 - Jared A. Beekman, Robert Michael Owens, Mary Jane Irwin:
Mesh Arrays and LOGICIAN: A Tool for Their Efficient Generation. DAC 1987: 357-362 - Rajiv Bhateja, Randy H. Katz:
VALKYRIE: A Validation Subsystem of a Version Server for Computer-Aided Design Data. DAC 1987: 321-327 - M. L. Brei:
Needed: A Meta-Language for Evaluating the Expressiveness of EDIF, IGES, VHDL and Other Representation Mechanisms. DAC 1987: 565-565 - Forrest Brewer, Daniel Gajski:
Knowledge Based Control in Micro-Architecture Design. DAC 1987: 203-209 - Randal E. Bryant, Derek L. Beatty, Karl S. Brace, Kyeongsoon Cho, Thomas J. Sheffler:
COSMOS: A Compiled Simulator for MOS Circuits. DAC 1987: 9-16 - Dick C. A. Bulterman:
CASE: An Integrated Design Environment for Algorithm-Driven Architectures. DAC 1987: 596-599 - Robert E. Canright, A. R. Helland:
Reflections of High Speed Signals Analyzed as a Delay in Timing for Clocked Logic. DAC 1987: 133-139 - Clyde W. Carpenter, Mark Horowitz:
Generating Incremental VLSI Compaction Spacing Constraints. DAC 1987: 291-297 - T. Cesear, E. Iodice, C. Tsareff:
PAMS: An Expert System for Parameterized Module Synthesis. DAC 1987: 666-671 - Susheel J. Chandra, Janak H. Patel:
A Hierarchical Approach Test Vector Generation. DAC 1987: 495-501 - Mandalagiri S. Chandrasekhar, J. P. Privitera, K. W. Conradt:
Application of Term Rewriting Techniques to Hardware Design Verification. DAC 1987: 277-282 - Y.-C. Chang, S. C. Chang, L.-H. Hsu:
Automated Layout Generation Using Gate Matrix Approach. DAC 1987: 552-558 - H. H. Chen:
Routing L-Shaped Channels in Nonslicing-Structure Placement. DAC 1987: 152-158 - John S. J. Chen, David Y. Chen:
A Design Rule Independent Cell Compiler. DAC 1987: 466-471 - Mely Chen Chi:
An Automatic Rectilinear Partitioning Procedure for Standard Cells. DAC 1987: 50-55 - S. Chowdhury:
An Automated Design of Minimum-Area IC Power/Ground Nets. DAC 1987: 223-229 - Robert K. Chun, Keh-Jeng Chang, Lawrence P. McNamee:
VISION: VHDL Induced Schematic Imaging on Net-Lists. DAC 1987: 436-442 - Mehmet A. Cirit:
Transistor Sizing in CMOS Circuits. DAC 1987: 121-124 - S. E. Concina, G. S. Liu:
Integrating Design Information for IC Diagnosis. DAC 1987: 251-257 - Wayne Wei-Ming Dai, Masao Sato, Ernest S. Kuh:
A Dynamic and Efficient Representation of Building-Block Layout. DAC 1987: 376-384 - Louis-Philippe Demers, P. Jacques, S. Fauvel, Eduard Cerny:
CHESHIRE: An Object-Oriented Integration of VLSI CAD Tools. DAC 1987: 750-756 - Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton:
On the Verification of Sequential Machines at Differing Levels of Abstraction. DAC 1987: 271-276 - Jeremy Dion:
Fast Printed Circuit Board Routing. DAC 1987: 727-734 - Norman J. Elias:
A Case Study in Silicon Compilation Software Engineering, HVDEV High Voltage Device Layout Generator. DAC 1987: 82-88 - Richard J. Enbody, Hung-Chang Du:
General Purpose Router. DAC 1987: 637-640 - Nikrouz Faroughi, Michael A. Shanblatt:
An Improved Systematic Method for Constructing Systolic Arrays from Algorithms. DAC 1987: 26-34 - R. Forbes:
Heuristic Acceleration of Force-Directed Placement. DAC 1987: 735-740
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