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Publication search results
found 68 matches
- 2004
- Jason Helge Anderson, Farid N. Najm, Tim Tuan:
Active leakage power optimization for FPGAs. FPGA 2004: 33-41 - Sashisu Bajracharya, Chang Shu, Kris Gaj, Tarek A. El-Ghazawi:
Implementation of elliptic curve cryptosystems over GF(2n) in optimal normal basis on a reconfigurable computer. FPGA 2004: 259 - Zachary K. Baker, Viktor K. Prasanna:
Time and area efficient pattern matching on FPGAs. FPGA 2004: 223-232 - Paul Berube, José Nelson Amaral, Mike H. MacGregor:
An FPGA prototype for the experimental evaluation of a multizone network cache. FPGA 2004: 253 - Gabriel Caffarena, Slobodan Bojanic, Juan A. López, Carlos E. Pedreira, Octavio Nieto-Taladriz:
High-speed systolic array for gene matching. FPGA 2004: 248 - Richard Carbone, Andreas E. Savakis:
A flexible hardware architecture for 2-D discrete wavelet transform. FPGA 2004: 246 - Mark L. Chang, Scott Hauck:
Least-significant bit optimization techniques for FPGAs. FPGA 2004: 251 - Deming Chen, Jason Cong, Fei Li, Lei He:
Low-power technology mapping for FPGA architectures with dual supply voltages. FPGA 2004: 109-117 - Wang Chen, Panos Kosmas, Miriam Leeser, Carey M. Rappaport:
An FPGA implementation of the two-dimensional finite-difference time-domain (FDTD) algorithm. FPGA 2004: 213-222 - Erik Chmelar:
Subframe multiplexing for FPGA manufacturing test configuration. FPGA 2004: 245 - Katherine Compton, Scott Hauck:
Flexibility measurement of domain-specific reconfigurable hardware. FPGA 2004: 155-161 - Jason Cong, Yiping Fan, Guoling Han, Zhiru Zhang:
Application-specific instruction generation for configurable processor architectures. FPGA 2004: 183-189 - Tomasz S. Czajkowski, Jonathan Rose:
A synthesis oriented omniscient manual editor. FPGA 2004: 89-98 - Martin Danek, Josef Kolár:
FPGA modelling for high-performance algorithms. FPGA 2004: 251 - André DeHon, Brad L. Hutchings, Daryl Rudusky, James Hwang, Nikhil, Salil Raje, Adrian Stoica:
What is the right model for programming and using modern FPGAs? FPGA 2004: 119 - André DeHon, Michael J. Wilson:
Nanowire-based sublithographic programmable logic arrays. FPGA 2004: 123-132 - Daniel Denning, Malachy Devlin, James Irvine:
Hardware co-simulation in system generator of the AES-128 encryption algorithm. FPGA 2004: 247 - Christopher C. Doss, Robert L. Riley Jr.:
FPGA-based implementation of single-precision exponential unit. FPGA 2004: 248 - Steve Ferrera, Nicholas P. Carter:
A magnetoelectronic macrocell employing reconfigurable threshold logic. FPGA 2004: 143-151 - Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis:
A novel coarse-grain reconfigurable data-path for accelerating DSP kernels. FPGA 2004: 252 - Aman Gayasen, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan:
Reducing leakage energy in FPGAs using region-constrained placement. FPGA 2004: 51-58 - Zhi Guo, Walid A. Najjar, Frank Vahid, Kees A. Vissers:
A quantitative analysis of the speedup factors of FPGAs over processors. FPGA 2004: 162-170 - Jong-Ru Guo, Chao You, Michael Chu, Robert W. Heikaus, Kuan Zhou, Okan Erdogan, Jiedong Diao, Bryan S. Goda, Russell P. Kraft, John F. McDonald:
The gigahertz FPGA: design consideration and applications. FPGA 2004: 248 - Christian Hinkelbein, Andrei Khomich, Andreas Kugel, Reinhard Männer, Matthias Müller:
Using an FPGA coprocessor for improving execution speed of TRT-LUT: one of the feature extraction algorithms for ATLAS LVL2 trigger. FPGA 2004: 247 - Ranjesh G. Jaganathan, Matthew Simpson, Ron Sass:
Automatic discovery, selection, and specialization of modules in RCADE. FPGA 2004: 256 - Tianyi Jiang, Xiaoyong Tang, Prithviraj Banerjee:
High level area, delay and power estimation for FPGAs. FPGA 2004: 249 - Takashi Kawanami, Masakazu Hioki, Hiroshi Nagase, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike:
Preliminary performance analysis of flex power FPGA, a power reconfigurable device with fine granularity. FPGA 2004: 257 - John F. Keane, Christopher Bradley, Carl Ebeling:
A compiled accelerator for biological cell signaling simulations. FPGA 2004: 233-241 - Paul Kohlbrenner, Kris Gaj:
An embedded true random number generator for FPGAs. FPGA 2004: 71-78 - Rohini Krishnan, José Pineda de Gyvez, Martijn T. Bennebroek:
Low energy FPGA interconnect design. FPGA 2004: 255
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retrieved on 2024-03-28 12:34 CET from data curated by the dblp team
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