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Publication search results
found 104 matches
- 1997
- Alberto Allara, S. Filipponi, William Fornaciari, Fabio Salice, Donatella Sciuto:
Improving Design Turnaround Time via Two-Levels Hw/Sw Co-Simulation. ICCD 1997: 400-405 - Karim Arabi, Bozena Kaminska:
Built-In Temperature Sensors for On-line Thermal Monitoring of Microelectronic Structures. ICCD 1997: 462-467 - Ravishankar Arunachalam, Florentin Dartu, Lawrence T. Pileggi:
CMOS Gate Delay Models for General RLC Loading. ICCD 1997: 224-229 - M. Bacis, Giacomo Buonanno, Fabrizio Ferrandi, Franco Fummi, Luca Gerli, Donatella Sciuto:
Application of a Testing Framework to VHDL Descriptions at Different Abstraction Levels. ICCD 1997: 654-658 - Gabriel P. Bischoff, Karl S. Brace, Samir Jain, Rahul Razdan:
Formal Implementation Verification of the Bus Interface Unit for the Alpha 21264 Microprocessor. ICCD 1997: 16-24 - Ronald D. Blanton, John P. Hayes:
Properties of the Input Pattern Fault Model. ICCD 1997: 372-380 - Cristiana Bolchini, Donatella Sciuto, Fabio Salice:
A TSC Evaluation Function for Combinational Circuits. ICCD 1997: 555-560 - David S. Bormann, Peter Y. K. Cheung:
Asnchronous Wrapper for Heterogeneous Systems. ICCD 1997: 307-314 - Maurício Breternitz Jr., Roger Smith:
Enhanced Compression Techniques to Simplify Programm Decompression and Execution. ICCD 1997: 170-176 - Bishop Brock, Warren A. Hunt Jr.:
Formally Specifying and Mechanically Verifying Programs for the Motorola Complex Arithmetic Processor DSP. ICCD 1997: 31-36 - Serban Bruma, Ralph H. J. M. Otten:
Novel Simulation of Deep-Submicron MOSFET Circuits. ICCD 1997: 62-67 - Erik Brunvand, Steven M. Nowick, Kenneth Y. Yun:
Practical Advances in Asynchronous Design. ICCD 1997: 662-668 - Carl Burch:
PA-8000: A Case Study of Static and Dynamic Branch Prediction. ICCD 1997: 97-105 - William Canfield, E. Allen Emerson, Avijit Saha:
Checking Formal Specifications under Simulation. ICCD 1997: 455-460 - Andreas C. Cangellaris, W. Pinello, Albert E. Ruehli:
Circuit-Based Description and Modeling of Electromagnetic Noise Effects in Packaged Low-Power Electronics. ICCD 1997: 136-142 - Robert Castañeda, Xiaodong Zhang, James M. Hoover Jr.:
A Comparative Evaluation of Hierarchical Network Architecture of the HP-Convex Exemplar. ICCD 1997: 258-266 - John A. Chandy, Prithviraj Banerjee:
A Parallel Circuit-Partitioned Algorithm for Timing Driven Cell Placement. ICCD 1997: 621-627 - Norman Chang, Valery Kanevsky, O. Sam Nakagawa, Khalid Rahmat, Soo-Young Oh:
Fast Generation of Statistically-based Worst-Case Modeling of On-Chip Interconnect. ICCD 1997: 720-725 - Yun-Nan Chang, Janardhan H. Satyanarayana, Keshab K. Parhi:
Design and Implementation of Low-Power Digit-Serial Multipliers. ICCD 1997: 186-195 - Chih-Tung Chen, Kayhan Küçükçakar:
An Architectural Power Optimization Case Study using High-level Synthesis. ICCD 1997: 562-570 - I-Cheng K. Chen, Chih-Chieh Lee, Trevor N. Mudge:
Instruction Prefetching Using Branch Prediction Information. ICCD 1997: 593-601 - I-Cheng K. Chen, Chih-Chieh Lee, Matt Postiff, Trevor N. Mudge:
Design Optimization for High-speed Per-address Two-level Branch Predictors. ICCD 1997: 88-96 - Benjamin Chen, Ivailo M. Nedelchev:
Power Compiler: A Gate-Level Power Optimization and Synthesis System. ICCD 1997: 74-79 - Jin Chen, Akhileswaran Ramachandran:
A Novel Test Set Design for Parametric Testing of Analog and Mixed-Signal Circuits. ICCD 1997: 474-480 - Fu-Chiung Cheng:
Synthesizing Iterative Functions into Delay-Insensitive Tree Circuits. ICCD 1997: 301-306 - Hoon Choi, Seung Ho Hwang:
Time-Stamped Transition Density for the Estimation of Delay Dependent Switching Activities. ICCD 1997: 68-73 - Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero:
A new Approach for Initialization Sequences Computation for Synchronous Sequential Circuits. ICCD 1997: 381-386 - Aurobindo Dasgupta, Shantanu Ganguly:
Divide & Conquer: A Strategy for Synthesis of Low Power Finite State Machines. ICCD 1997: 740-745 - Andrew Davey, David Lloyd:
An Evaluation of Asynchronous and Synchronous Design for Superscalar Architectures. ICCD 1997: 295-300 - Abhijit Dharchoudhury, David T. Blaauw, Joe Norton, Satyamurthy Pullela, J. Dunning:
Transistor-level Sizing and Timing Verification of Domino Circuits in the Power PC Microprocessor. ICCD 1997: 143-148
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