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Publication search results
found 128 matches
- 2016
- Cédric Marchand, Lilian Bossuet, Abdelkarim Cherkaoui:
Design and Characterization of the TERO-PUF on SRAM FPGAs. ISVLSI 2016: 134-139 - Zheng Wang, Alessandro Littarru, Emmanuel Ikechukwu Ugwu, Shazia Kanwal, Anupam Chattopadhyay:
Reliable Many-Core System-on-Chip Design Using K-Node Fault Tolerant Graphs. ISVLSI 2016: 619-624 - Maher Abdelrasoul, Mohammed Sharaf Sayed, Victor Goulart:
Scalable Integer DCT Architecture for HEVC Encoder. ISVLSI 2016: 314-318 - Monther Abusultan, Sunil P. Khatri:
A Ternary-Valued, Floating Gate Transistor-Based Circuit Design Approach. ISVLSI 2016: 719-724 - Tosiron Adegbija, Ann Gordon-Ross:
Phase-Based Dynamic Instruction Window Optimization for Embedded Systems. ISVLSI 2016: 397-402 - Innocent Agbo, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Praveen Raghavan, Francky Catthoor, Wim Dehaene:
Quantification of Sense Amplifier Offset Voltage Degradation due to Zero-and Run-Time Variability. ISVLSI 2016: 725-730 - S. Ahish, Dheeraj Sharma, M. H. Vasantha, Kumar Y. B. Nithin:
Design and Analysis of Novel InSb/Si Heterojunction Double Gate Tunnel Field Effect Transistor. ISVLSI 2016: 105-109 - Khadeer Ahmed, Amar Shrestha, Yanzhi Wang, Qinru Qiu:
System Design for In-Hardware STDP Learning and Spiking Based Probablistic Inference. ISVLSI 2016: 272-277 - Mohammed Alawad, Mingjie Lin:
Stochastic-Based Convolutional Networks with Reconfigurable Logic Fabric. ISVLSI 2016: 713-718 - Umar Albalawi, Saraju P. Mohanty, Elias Kougianos:
Energy-Efficient Design of the Secure Better Portable Graphics Compression Architecture for Trusted Image Communication in the IoT. ISVLSI 2016: 302-307 - Faris S. Alghareb, Mingjie Lin, Ronald F. DeMara:
Soft Error Effect Tolerant Temporal Self-Voting Checkers: Energy vs. Resilience Tradeoffs. ISVLSI 2016: 571-576 - Yousra Alkabani, Zach Koopmans, Haifeng Xu, Alex K. Jones, Rami G. Melhem:
Write Pulse Scaling for Energy Efficient STT-MRAM. ISVLSI 2016: 248-253 - Gayathri Ananthanarayanan, Smruti R. Sarangi, M. Balakrishnan:
Leakage Power Aware Task Assignment Algorithms for Multicore Platforms. ISVLSI 2016: 607-612 - Renzo Andri, Lukas Cavigelli, Davide Rossi, Luca Benini:
YodaNN: An Ultra-Low Power Convolutional Neural Network Accelerator Based on Binary Weights. ISVLSI 2016: 236-241 - Papa-Sidi Ba, Sophie Dupuis, Palanichamy Manikandan, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre:
Hardware Trust through Layout Filling: A Hardware Trojan Prevention Technique. ISVLSI 2016: 254-259 - Anjana Balachandran, Nandeesha Veeranna, Benjamin Carrión Schäfer:
On Time Redundancy of Fault Tolerant C-Based MPSoCs. ISVLSI 2016: 631-636 - Mario Barbareschi, Federico Iannucci, Antonino Mazzeo:
A Pruning Technique for B&B Based Design Exploration of Approximate Computing Variants. ISVLSI 2016: 707-712 - Vinamra Benara, Suresh Purini:
Accurus: A Fast Convergence Technique for Accuracy Configurable Approximate Adder Circuits. ISVLSI 2016: 577-582 - Oana Boncalo, Ioana Mot:
Multi Clock Flooded LDPC Decoding Architecture with Reduced Memory and Interconnect. ISVLSI 2016: 697-700 - Avik Bose, Prasun Ghosal, Saraju P. Mohanty:
STA: A Highly Scalable Low Latency Butterfly Fat Tree Based 3D NoC Design. ISVLSI 2016: 496-501 - Ruizhe Cai, Ao Ren, Yanzhi Wang, Bo Yuan:
Memristor-Based Discrete Fourier Transform for Improving Performance and Energy Efficiency. ISVLSI 2016: 643-648 - Giovanni Causapruno, Umberto Garlando, Fabrizio Cairo, Maurizio Zamboni, Mariagrazia Graziano:
A Reconfigurable Array Architecture for NML. ISVLSI 2016: 99-104 - Pratima Chatterjee, Mayukh Sarkar, Prasun Ghosal:
Computing in Ribosomes: Performing Boolean Logic Using mRNA-Ribosome System. ISVLSI 2016: 260-265 - Anupam Chattopadhyay, Vikramkumar Pudi, Anubhab Baksi, Thambipillai Srikanthan:
FPGA Based Cyber Security Protocol for Automated Traffic Monitoring Systems: Proposal and Implementation. ISVLSI 2016: 18-23 - Te-Hsuan Chen, John P. Hayes:
Design of Division Circuits for Stochastic Computing. ISVLSI 2016: 116-121 - Po-Tsang Chen, Ching-Yuan Yang:
A 90-nm CMOS Frequency Synthesizer with a Tripler for 60-GHz Wireless Communication Systems. ISVLSI 2016: 479-483 - Yuanchang Chen, Xinghua Yang, Fei Qiao, Jie Han, Qi Wei, Huazhong Yang:
A Multi-accuracy-Level Approximate Memory Architecture Based on Data Significance Analysis. ISVLSI 2016: 385-390 - Maria I. Mera Collantes, Mohamed El Massad, Siddharth Garg:
Threshold-Dependent Camouflaged Cells to Secure Circuits Against Reverse Engineering Attacks. ISVLSI 2016: 443-448 - Satyajit Das, Thomas Peyret, Kevin J. M. Martin, Gwenolé Corre, Mathieu Thevenin, Philippe Coussy:
A Scalable Design Approach to Efficiently Map Applications on CGRAs. ISVLSI 2016: 655-660 - Mark E. Dean, Christopher Daffron:
A VLSI Design for Neuromorphic Computing. ISVLSI 2016: 87-92
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