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Publication search results
found 93 matches
- 2004
- Anteneh A. Abbo, Richard P. Kleihorst, Vishal Choudhary, Leo Sevat:
Power Consumption of Performance-Scaled SIMD Processors. PATMOS 2004: 532-540 - Daniel A. Andersson, Lars J. Svensson, Per Larsson-Edefors:
On Skin Effect in On-Chip Interconnects. PATMOS 2004: 463-470 - Mark G. Arnold:
LPVIP: A Low-Power ROM-Less ALU for Low-Precision LNS. PATMOS 2004: 675-684 - David Atienza, Stylianos Mamagkakis, Francky Catthoor, Jose Manuel Mendias, Dimitrios Soudris:
Modular Construction and Power Modelling of Dynamic Memory Managers for Embedded Systems. PATMOS 2004: 510-520 - Fabricio B. Bastian, Cristiano Lazzari, José Luís Almada Güntzel, Ricardo Reis:
A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool. PATMOS 2004: 732-741 - Tobias Bjerregaard, Shankar Mahadevan, Jens Sparsø:
A Channel Library for Asynchronous Circuit Design Supporting Mixed-Mode Modeling. PATMOS 2004: 301-310 - Andrea Bona, Vittorio Zaccaria, Roberto Zafalon:
Low Effort, High Accuracy Network-on-Chip Power Macro Modeling. PATMOS 2004: 541-552 - Carlo Brandolese, William Fornaciari, Fabio Salice:
Discrete-Event Modeling and Simulation of Superscalar Microprocessor Architectures. PATMOS 2004: 238-247 - Marco Bucci, Michele Guglielmo, Raimondo Luzzi, Alessandro Trifiletti:
A Power Consumption Randomization Countermeasure for DPA-Resistant Cryptographic Processors. PATMOS 2004: 481-490 - Peter Caputa, Henrik Fredriksson, Martin Hansson, Stefan Back Andersson, Atila Alvandpour, Christer Svensson:
An Extended Transition Energy Cost Model for Buses in Deep Submicron Technologies. PATMOS 2004: 849-858 - Peter Celinski, Derek Abbott, Sorin Cotofana:
Delay Evaluation of High Speed Data-Path Circuits Based on Threshold Logic. PATMOS 2004: 899-906 - Hongliang Chang, Haifeng Qian, Sachin S. Sapatnekar:
The Certainty of Uncertainty: Randomness in Nanometer Design. PATMOS 2004: 36-47 - Howard Chen, Daniel L. Ostapko:
Modeling Temporal and Spatial Power Supply Voltage Variation for Timing Analysis. PATMOS 2004: 809-818 - Stefan Cserveny, Jean-Marc Masgonty, Christian Piguet:
Noise Margin in Low Power SRAM Cells. PATMOS 2004: 889-898 - Jean Michel Daga, Caroline Papaix, Marylene Combe, Emmanuel Racape, Vincent Sialelli:
Embedded EEPROM Speed Optimization Using System Power Supply Resources. PATMOS 2004: 381-391 - Carlo Dallavalle:
Adaptive Subthreshold Leakage Reduction Through N/P Wells Reverse Biasing. PATMOS 2004: 16 - Giorgos Dimitrakopoulos, Pavlos Kolovos, P. Kalogerakis, Dimitris Nikolos:
Design of High-Speed Low-Power Parallel-Prefix VLSI Adders. PATMOS 2004: 248-257 - Minh Quang Do, Per Larsson-Edefors, Lars Bengtsson:
Table-Based Total Power Consumption Estimation of Memory Arrays for Architects. PATMOS 2004: 869-878 - Nicola Dragone, Michele Quarantelli, Massimo Bertoletti, Carlo Guardiani:
High Yield Standard Cell Libraries: Optimization and Modeling. PATMOS 2004: 129-137 - Christos Drosos, Labros Bisdounis, Dimitris Metafas, Spyros Blionas, Anna Tatsaki:
A Multi-level Validation Methodology for Wireless Network Applications. PATMOS 2004: 332-341 - Jürgen Fischer, Ettore Amirante, Agnese Bargagli-Stoffi, Philip Teichmann, Dominik Gruber, Doris Schmitt-Landsiedel:
Power Supply Net for Adiabatic Circuits. PATMOS 2004: 413-422 - Uri Frank, Ran Ginosar:
A Predictive Synchronizer for Periodic Clock Domains. PATMOS 2004: 402-412 - Jingjing Fu, Zuying Luo, Xianlong Hong, Yici Cai, Sheldon X.-D. Tan, Zhu Pan:
Simultaneous Wire Sizing and Decoupling Capacitance Budgeting for Robust On-Chip Power Delivery. PATMOS 2004: 433-441 - Kazuki Fukuoka, Masaaki Iijima, Kenji Hamada, Masahiro Numa, Akira Tada:
A Novel Layout Approach Using Dual Supply Voltage Technique on Body-Tied PD-SOI. PATMOS 2004: 423-432 - Michalis D. Galanis, George Theodoridis, Spyros Tragoudas, Dimitrios Soudris, Constantinos E. Goutis:
Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path. PATMOS 2004: 652-661 - Tobias Gemmeke, Tobias G. Noll:
A Physically Oriented Model to Quantify the Noise-on-Delay Effect. PATMOS 2004: 879-888 - Patricia Guitton-Ouhamou, Hanene Ben Fradj, Cécile Belleudy, Michel Auguin:
Low Power Co-design Tool and Power Optimization of Schedules and Memory System. PATMOS 2004: 603-612 - Ilham Hassoune, Amaury Nève, Jean-Didier Legat, Denis Flandre:
Investigation of Low-Power Low-Voltage Circuit Techniques for a Hybrid Full-Adder Cell. PATMOS 2004: 189-197 - Domenik Helms, Eike Schmidt, Wolfgang Nebel:
Leakage in CMOS Circuits - An Introduction. PATMOS 2004: 17-35 - Stephan Henzler, Georg Georgakos, Jörg Berthold, Doris Schmitt-Landsiedel:
Single Supply Voltage High-Speed Semi-dynamic Level-Converting Flip-Flop with Low Power and Area Consumption. PATMOS 2004: 392-401
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