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Publication search results
found 196 matches
- 2016
- Ahmet Abaci, Erkan Yüce:
Second-Order Voltage-Mode Universal Filters Using Two DVCCs, Two Grounded Capacitors and Four Resistors. J. Circuits Syst. Comput. 25(12): 1650154:1-1650154:15 (2016) - Zine Abid, Dalia A. El-Dib, Rizwan Mudassir:
Modified Operand Decomposition Multiplication for High Performance Parallel Multipliers. J. Circuits Syst. Comput. 25(12): 1650149:1-1650149:12 (2016) - Rekha Agrawal, Shailendra Jain:
Suitability of Reduced Part Count Multilevel Inverter Topologies for Grid Interfacing. J. Circuits Syst. Comput. 25(7): 1650081:1-1650081:18 (2016) - Rekha Agrawal, Shailendra Jain:
A Review of Some Recently Proposed Topologies for Multilevel DC-AC Conversion. J. Circuits Syst. Comput. 25(12): 1650157:1-1650157:25 (2016) - Meysam Akbari, Omid Hashemipour:
Multi-Path Class AB Operational Amplifier with High Performance for SC Circuits. J. Circuits Syst. Comput. 25(11): 1650144:1-1650144:14 (2016) - Ali Akhavan, Hamid Reza Mohammadi:
A Comprehensive Approach for Control of Grid-Connected Quasi-Z-Source Cascaded Multilevel Inverters. J. Circuits Syst. Comput. 25(5) (2016) - Syed Iftekhar Ali, Md. Shafiqul Islam, Mohammad Rakibul Islam:
A Comprehensive Review of Energy Efficient Content Addressable Memory Circuits for Network Applications. J. Circuits Syst. Comput. 25(4): 1630002:1-1630002:40 (2016) - Juan Antonio Aqui-Tapia, Mario Ponce-Silva, Victor Hugo Olivares-Peregrino, Marco Antonio Oliver-Salazar, Claudia Cortés-García:
Assessment of the Bootstrap Technique in Single-Phase Current-Fed Full-Bridge Resonant Inverters with Reactive Energy. J. Circuits Syst. Comput. 25(11): 1650141:1-1650141:12 (2016) - S. P. Valan Arasu, S. Baulkani:
An Efficient FPGA Architecture with High-Performance 2D DWT Processor for Medical Imaging. J. Circuits Syst. Comput. 25(9): 1650110:1-1650110:22 (2016) - Daniel Arbet, Gabriel Nagy, Martin Kovác, Viera Stopjaková:
Fully Differential Difference Amplifier for Low-Noise and Low-Distortion Applications. J. Circuits Syst. Comput. 25(3): 1640019:1-1640019:18 (2016) - Pouya Asadi:
A New Array Multiplier Using an Optimized Carry Network and Dynamic CMOS Technology. J. Circuits Syst. Comput. 25(2): 1650004:1-1650004:15 (2016) - Florence Azaïs, Stephane David-Grignot, Laurent Latorre, Francois Lefevre:
Digital Embedded Test Instrument for On-Chip Phase Noise Testing of Analog/RF Integrated Circuits. J. Circuits Syst. Comput. 25(3): 1640014:1-1640014:18 (2016) - Ebrahim Babaei, Sara Laali:
New Extendable 15-Level Basic Unit for Multilevel Inverters. J. Circuits Syst. Comput. 25(12): 1650151:1-1650151:22 (2016) - Raed Bani-Hani, Khaldoon Mhaidat, Salah S. Harb:
Very Compact and Efficient 32-Bit AES Core Design Using FPGAs for Small-Footprint Low-Power Embedded Applications. J. Circuits Syst. Comput. 25(7): 1650080:1-1650080:17 (2016) - Mohamed Ben-Esmael, Mary Mathew, Bryan L. Hart, Khaled Hayatleh:
Technique for Increasing the Output Impedance of CMOS Regulated Cascode Circuits. J. Circuits Syst. Comput. 25(10): 1650118:1-1650118:6 (2016) - Marcelo Daniel Berejuck, Antônio Augusto Fröhlich:
Evaluation of a Connectionless Technique for System-on-Chip Interconnection. J. Circuits Syst. Comput. 25(10): 1630005:1-1630005:26 (2016) - Anupam Bhar, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur:
Small Test Set Generation with High Diagnosability. J. Circuits Syst. Comput. 25(4): 1650024:1-1650024:18 (2016) - Bülent Bilgehan, Bugçe Eminaga, Mustafa Riza:
New Solution Method for Electrical Systems Represented by Ordinary Differential Equation. J. Circuits Syst. Comput. 25(2): 1650011:1-1650011:20 (2016) - N. V. Vijaya Krishna Boppana, Saiyu Ren:
A Low-Power and Area-Efficient 64-Bit Digital Comparator. J. Circuits Syst. Comput. 25(12): 1650148:1-1650148:15 (2016) - Daniel Mealha Cabrita, Carlos Raimundo Erig Lima:
A Fast Simulator in FPGA for LUT-Based Combinational Logic Circuits of Arbitrary Topology for Evolutionary Algorithms. J. Circuits Syst. Comput. 25(2): 1650009:1-1650009:23 (2016) - Meili Cao, Haizhen He, Hairong Lin, Hao Peng, Bohui Zhu:
Current-Mode nth-Order Filter Based on a Minimal Component. J. Circuits Syst. Comput. 25(5): 1650035:1-1650035:14 (2016) - Sevilay Cetin:
An Improved Zero Voltage Transition PWM Boost Converter with an Active Snubber Cell. J. Circuits Syst. Comput. 25(10): 1650128:1-1650128:23 (2016) - Changyuan Chang, Xiaomin Huang, Yuanye Li, Yao Chen:
High-Precision Digital Constant Current Controller with Demagnetization-Time Compensation for Primary-Side Regulation Flyback Converter. J. Circuits Syst. Comput. 25(8): 1650095:1-1650095:17 (2016) - Chip-Hong Chang, Tae-Hyoung Kim, Hao Yu:
Editorial. J. Circuits Syst. Comput. 25(1): 1602001:1-1602001:5 (2016) - Chia-Lun Chang, Tai-Cheng Lee:
A Compact Multi-Input Power Conversion System with High Time-Efficiency Inductor-Sharing Technique for Thermoelectric Energy Harvesting Applications. J. Circuits Syst. Comput. 25(1): 1640007:1-1640007:18 (2016) - Gang Chen, Kai Huang, Long Cheng, Biao Hu, Alois C. Knoll:
Dynamic Partitioned Cache Memory for Real-Time MPSoCs with Mixed Criticality. J. Circuits Syst. Comput. 25(6): 1650062:1-1650062:17 (2016) - Hung-Chun Chien:
Switch-Controllable Full-Phase Operation Precision Half-Wave Rectifier Using a Single OTRA. J. Circuits Syst. Comput. 25(7): 1650070:1-1650070:21 (2016) - Bruno Felipe Costa, Taufik Abrão:
MIMO Precoding for Correlated Fading Channels. J. Circuits Syst. Comput. 25(5): 1650041:1-1650041:11 (2016) - Yingnan Cui, Wei Zhang, Vivek Chaturvedi, Weichen Liu, Bingsheng He:
Thermal-Aware Task Scheduling for 3D-Network-on-Chip: A Bottom to Top Scheme. J. Circuits Syst. Comput. 25(1): 1640003:1-1640003:20 (2016) - Quoc Khanh Dang, Young Soo Suh:
A Sensor-Fusing System for Spatial Circle and Trunk Parameter Estimation. J. Circuits Syst. Comput. 25(10): 1650117:1-1650117:22 (2016)
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