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Publication search results
found 149 matches
- 1996
- Michael J. Alexander, Gabriel Robins:
New performance-driven FPGA routing algorithms. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(12): 1505-1517 (1996) - Narayan R. Aluru, Kincho H. Law, Robert W. Dutton:
Simulation of the hydrodynamic device model on distributed memory parallel computers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(9): 1029-1047 (1996) - Narain D. Arora, Kartik V. Raol, Reinhard Schumann, Llanda M. Richardson:
Modeling and extraction of interconnect capacitances for multilayer VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(1): 58-67 (1996) - Martin Bächtold, Jan G. Korvink, Henry Baltes:
Enhanced multipole acceleration technique for the solution of large Poisson computations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(12): 1541-1546 (1996) - William R. Bandy, Raymond S. Winton:
A new approach for modeling the MOSFET using a simple, continuous analytical expression for drain conductance which includes velocity-saturation in a fundamental way. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(5): 475-483 (1996) - Peter A. Beerel, Cheng-Ta Hsieh, Suhrid A. Wadekar:
Estimation of energy consumption in speed-independent control circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(6): 672-680 (1996) - Luca Benini, Giovanni De Micheli:
Automatic synthesis of low-power gated-clock finite-state machines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(6): 630-643 (1996) - Michel R. C. M. Berkelaar, Pim H. W. Buurman, Jochen A. G. Jess:
Computing the entire active area/power consumption versus delay tradeoff curve for gate sizing with a piecewise linear simulator. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(11): 1424-1434 (1996) - Jochen Bern, Christoph Meinel, Anna Slobodová:
Some heuristics for generating tree-like FBDD types. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(1): 127-130 (1996) - Jochen Bern, Christoph Meinel, Anna Slobodová:
Global rebuilding of OBDD's avoiding memory requirement maxima. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(1): 131-134 (1996) - Sandeep Bhatia, Niraj K. Jha:
Synthesis for parallel scan: applications to partial scan and robust path-delay fault testability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(2): 228-243 (1996) - Subhrajit Bhattacharya, Sujit Dey, Franc Brglez:
Fast true delay estimation during high level synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(9): 1088-1105 (1996) - Yves Blaquière, Michel R. Dagenais, Yvon Savaria:
Timing analysis speed-up using a hierarchical and a multimode approach. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(2): 244-255 (1996) - Guy Bois, Eduard Cerny:
Efficient generation of diagonal constraints for 2-D mask compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(9): 1119-1126 (1996) - Manjit Borah, Robert Michael Owens, Mary Jane Irwin:
Transistor sizing for low power CMOS circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(6): 665-671 (1996) - Robert C. Carden IV, Jianmin Li, Chung-Kuan Cheng:
A global router with a theoretical bound on the optimal solution. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(2): 208-216 (1996) - Robert J. Carragher, Chung-Kuan Cheng, Xiao-Ming Xiong, Masahiro Fujita, Ramamohan Paturi:
Solving the net matching problem in high-performance chip design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(8): 902-911 (1996) - Kevin Cattell, Jon C. Muzio:
Synthesis of one-dimensional linear hybrid cellular automata. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(3): 325-335 (1996) - Krishnendu Chakrabarty, John P. Hayes:
Test response compaction using multiplexed parity trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(11): 1399-1408 (1996) - Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien:
Spectral-based multiway FPGA partitioning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(5): 554-560 (1996) - Shih-Chieh Chang, Malgorzata Marek-Sadowska, Kwang-Ting Cheng:
Perturb and simplify: multilevel Boolean network optimizer. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(12): 1494-1504 (1996) - Shih-Chieh Chang, Malgorzata Marek-Sadowska, TingTing Hwang:
Technology mapping for TLU FPGAs based on decomposition of binary decision diagrams. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(10): 1226-1236 (1996) - Chih-Ang Chen, Sandeep K. Gupta:
Design of efficient BIST test pattern generators for delay testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(12): 1568-1575 (1996) - Y. G. Chen, James B. Kuo:
A unified triode/saturation model with an improved continuity in the output conductance suitable for CAD of VLSI circuits using deep sub-0.1 µm NMOS devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(2): 256-258 (1996) - Hsiao-Feng Steven Chen, D. T. Lee:
A faster algorithm for rubber-band equivalent transformation for planar VLSI layouts. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(2): 217-227 (1996) - Cheng-Hsi Chen, Ioannis G. Tollis:
An Omega(k2) lower bound for area optimization of spiral floorplans. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(3): 358-360 (1996) - Kwang-Ting Cheng, Hsi-Chuan Chen:
Classification and identification of nonrobust untestable path delay faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(8): 845-853 (1996) - Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Massimo Poncino, Fabio Somenzi:
Automatic state space decomposition for approximate FSM traversal based on circuit analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(12): 1451-1464 (1996) - Hyunwoo Cho, Gary D. Hachtel, Enrico Macii, Bernard Plessier, Fabio Somenzi:
Algorithms for approximate FSM traversal based on state space decomposition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(12): 1465-1478 (1996) - Tan-Li Chou, Kaushik Roy:
Estimation of activity for static and domino CMOS circuits considering signal correlations and simultaneous switching. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(10): 1257-1265 (1996)
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