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Publication search results
found 199 matches
- 2021
- Abhijit Das, John Jose, Prabhat Mishra:
Data Criticality in Multithreaded Applications: An Insight for Many-Core Systems. IEEE Trans. Very Large Scale Integr. Syst. 29(9): 1675-1679 (2021) - Meysam Akbari, Safwan Mawlood Hussein, Yasir Hashim, Kea-Tiong Tang:
An Enhanced Input Differential Pair for Low-Voltage Bulk-Driven Amplifiers. IEEE Trans. Very Large Scale Integr. Syst. 29(9): 1601-1611 (2021) - Tanfer Alan, Andreas Gerstlauer, Jörg Henkel:
Cross-Layer Approximate Hardware Synthesis for Runtime Configurable Accuracy. IEEE Trans. Very Large Scale Integr. Syst. 29(6): 1231-1243 (2021) - Abdulrahman Alaql, Md. Moshiur Rahman, Swarup Bhunia:
SCOPE: Synthesis-Based Constant Propagation Attack on Logic Locking. IEEE Trans. Very Large Scale Integr. Syst. 29(8): 1529-1542 (2021) - Massimo Alioto:
Opening of the 2021 Editorial Year - Overture for a New Year of Change. IEEE Trans. Very Large Scale Integr. Syst. 29(1): 1-2 (2021) - Massimo Alioto:
Second Quarter of the 2021 Editorial Year - A Year in Crescendo. IEEE Trans. Very Large Scale Integr. Syst. 29(5): 815-842 (2021) - Abdullah Aljuffri, Marc Zwalua, Cezar Rodolfo Wedig Reinbrecht, Said Hamdioui, Mottaqiallah Taouil:
Applying Thermal Side-Channel Attacks on Asymmetric Cryptography. IEEE Trans. Very Large Scale Integr. Syst. 29(11): 1930-1942 (2021) - Turki Alnuayri, S. Saqib Khursheed, Antonio Leonel Hernández Martínez, Daniele Rossi:
Differential Aging Sensor Using Subthreshold Leakage Current to Detect Recycled ICs. IEEE Trans. Very Large Scale Integr. Syst. 29(12): 2064-2075 (2021) - Abdolah Amirany, Kian Jafari, Mohammad Hossein Moaiyeri:
High-Performance Spintronic Nonvolatile Ternary Flip-Flop and Universal Shift Register. IEEE Trans. Very Large Scale Integr. Syst. 29(5): 916-924 (2021) - Charalampos Antoniadis, Nestor E. Evmorfopoulos, Georgios I. Stamoulis:
Graph-Based Sparsification and Synthesis of Dense Matrices in the Reduction of RLC Circuits. IEEE Trans. Very Large Scale Integr. Syst. 29(3): 580-590 (2021) - Yuri Ardesi, Giovanna Turvani, Mariagrazia Graziano, Gianluca Piccinini:
SCERPA Simulation of Clocked Molecular Field-Coupling Nanocomputing. IEEE Trans. Very Large Scale Integr. Syst. 29(3): 558-567 (2021) - Aqeeb Iqbal Arka, Biresh Kumar Joardar, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty:
Performance and Accuracy Tradeoffs for Training Graph Neural Networks on ReRAM-Based Architectures. IEEE Trans. Very Large Scale Integr. Syst. 29(10): 1743-1756 (2021) - Neelam Arya, Manisha Pattanaik, G. K. Sharma:
Energy-Efficient Logarithmic Square Rooter for Error-Resilient Applications. IEEE Trans. Very Large Scale Integr. Syst. 29(11): 1994-1997 (2021) - Kimia Zamiri Azar, Hadi Mardani Kamali, Shervin Roshanisefat, Houman Homayoun, Christos P. Sotiriou, Avesta Sasan:
Data Flow Obfuscation: A New Paradigm for Obfuscating Circuits. IEEE Trans. Very Large Scale Integr. Syst. 29(4): 643-656 (2021) - Sarah Azimi, Corrado De Sio, Luca Sterpone:
A Radiation-Hardened CMOS Full-Adder Based on Layout Selective Transistor Duplication. IEEE Trans. Very Large Scale Integr. Syst. 29(8): 1596-1600 (2021) - Milad Bahadori, Kimmo Järvinen, Valtteri Niemi:
FPGA Implementations of 256-Bit SNOW Stream Ciphers for Postquantum Mobile Security. IEEE Trans. Very Large Scale Integr. Syst. 29(11): 1943-1954 (2021) - Sanmitra Banerjee, Arjun Chaudhuri, August Ning, Krishnendu Chakrabarty:
Variation-Aware Delay Fault Testing for Carbon-Nanotube FET Circuits. IEEE Trans. Very Large Scale Integr. Syst. 29(2): 409-422 (2021) - Saambhavi Baskaran, Jack Sampson:
Evaluation of Tradeoffs in the Design of FPGA Fabrics Using Electrostrictive 2-D FETs. IEEE Trans. Very Large Scale Integr. Syst. 29(4): 691-701 (2021) - Heiner Bauer, Sebastian Höppner, Chris Paul Iatrou, Zohra Charania, Stephan Hartmann, Saif-Ur Rehman, Andreas Dixius, Georg Ellguth, Dennis Walter, Johannes Uhlig, Felix Neumärker, Marc Berthel, Marco Stolba, Florian Kelber, Leon Urbas, Christian Mayr:
Hardware Implementation of an OPC UA Server for Industrial Field Devices. IEEE Trans. Very Large Scale Integr. Syst. 29(11): 1998-2002 (2021) - Biswajit Bhowmik:
Dugdugi: An Optimal Fault Addressing Scheme for Octagon-Like On-Chip Communication Networks. IEEE Trans. Very Large Scale Integr. Syst. 29(5): 1009-1021 (2021) - Seyfeddine Boukhtache, Benoît Blaysat, Michel Grédiac, François Berry:
Alternatives to Bicubic Interpolation Considering FPGA Hardware Resource Consumption. IEEE Trans. Very Large Scale Integr. Syst. 29(2): 247-258 (2021) - Alvaro Cintas Canto, Mehran Mozaffari Kermani, Reza Azarderakhsh:
Reliable CRC-Based Error Detection Constructions for Finite Field Multipliers With Applications in Cryptography. IEEE Trans. Very Large Scale Integr. Syst. 29(1): 232-236 (2021) - Alvaro Cintas Canto, Mehran Mozaffari Kermani, Reza Azarderakhsh:
CRC-Based Error Detection Constructions for FLT and ITA Finite Field Inversions Over GF(2m). IEEE Trans. Very Large Scale Integr. Syst. 29(5): 1033-1037 (2021) - Hongbo Cao, Faqiang Wang:
Spreading Operation Frequency Ranges of Memristor Emulators via a New Sine-Based Method. IEEE Trans. Very Large Scale Integr. Syst. 29(4): 617-630 (2021) - Firat Celik, Ayca Akkaya, Armin Tajalli, Yusuf Leblebici:
A 32-Gb/s PAM-4 SST Transmitter With Four-Tap FFE Using High-Impedance Driver in 28-nm FDSOI. IEEE Trans. Very Large Scale Integr. Syst. 29(6): 1132-1140 (2021) - Francesco Centurelli, Giuseppe Scotti, Gaetano Palumbo:
A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n- and p-type Flip-Flops. IEEE Trans. Very Large Scale Integr. Syst. 29(5): 998-1008 (2021) - Anirban Chakraborty, Ayan Banerjee:
CORDIC-Based High-Speed VLSI Architecture of Transform Model Estimation for Real-Time Imaging. IEEE Trans. Very Large Scale Integr. Syst. 29(1): 215-226 (2021) - Hsun-Wei Chan, Wei-Che Lee, Kang-Lun Chiu, Chih-Wei Jen, Shyh-Jye Jou:
A Digital Two-Stage Phase Noise Compensation and rCFO/rSCO Tracking Module for mmW Single Carrier Systems. IEEE Trans. Very Large Scale Integr. Syst. 29(5): 904-915 (2021) - Libo Chang, Shengbing Zhang, Huimin Du, Yue Chen, Shiyu Wang:
A Reconfigurable Neural Network Processor With Tile-Grained Multicore Pipeline for Object Detection on FPGA. IEEE Trans. Very Large Scale Integr. Syst. 29(11): 1967-1980 (2021) - Rohit B. Chaurasiya, Rahul Shrestha:
A New Hardware-Efficient Spectrum-Sensor VLSI Architecture for Data-Fusion-Based Cooperative Cognitive-Radio Network. IEEE Trans. Very Large Scale Integr. Syst. 29(4): 760-773 (2021)
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