Po-Chuan Lin

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

◀ ▶ joint publications with Ta-Wen Kuan

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Publications

2015
[j8]
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  - journals/iet-cdt/PengLBWPBK15
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  - https://dblp.org/rec/journals/iet-cdt/PengLBWPBK15
Chih-Hsiang Peng, Po-Chuan Lin, Shovan Barma, Jhing-Fa Wang, Hong-Yuan Peng, K. Bharanitharan, Ta-Wen Kuan:
Low-power enhanced system-on-chip design for sequential minimal optimisation learning core with tri-layer bus and butterfly-path accelerator. IET Comput. Digit. Tech. 9(2): 93-100 (2015)
[j7]
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  - journals/iet-cdt/ChouKLCW15
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Chih-Hung Chou, Ta-Wen Kuan, Po-Chuan Lin, Bo-Wei Chen, Jhing-Fa Wang:
Memory-efficient buffering method and enhanced reference template for embedded automatic speech recognition system. IET Comput. Digit. Tech. 9(3): 153-164 (2015)
[j6]
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  - journals/tvlsi/PengKLWW15
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Chih-Hsiang Peng, Ta-Wen Kuan, Po-Chuan Lin, Jhing-Fa Wang, Guo-Ji Wu:
Trainable and Low-Cost SMO Pattern Classifier Implemented via MCMC and SFBS Technologies. IEEE Trans. Very Large Scale Integr. Syst. 23(10): 2295-2306 (2015)
2014
[j5]
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  - journals/tvlsi/PengCKLWS14
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Chih-Hsiang Peng, Bo-Wei Chen, Ta-Wen Kuan, Po-Chuan Lin, Jhing-Fa Wang, Nai-Sheng Shih:
REC-STA: Reconfigurable and Efficient Chip Design With SMO-Based Training Accelerator. IEEE Trans. Very Large Scale Integr. Syst. 22(8): 1791-1802 (2014)
2012
[j4]
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  - journals/tvlsi/KuanWWLG12
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  - https://dblp.org/rec/journals/tvlsi/KuanWWLG12
Ta-Wen Kuan, Jhing-Fa Wang, Jia-Ching Wang, Po-Chuan Lin, Gaung-Hui Gu:
VLSI Design of an SVM Learning Core on Sequential Minimal Optimization Algorithm. IEEE Trans. Very Large Scale Integr. Syst. 20(4): 673-683 (2012)
2011
[c3]
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  - conf/smc/WangPWLK11
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Jhing-Fa Wang, Jr-Shiang Peng, Jia-Ching Wang, Po-Chuan Lin, Ta-Wen Kuan:
Hardware/software co-design for fast-trainable speaker identification system based on SMO. SMC 2011: 1621-1625

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