BibTeX record journals/tcad/SathyamurthySF98

download as .bib file

@article{DBLP:journals/tcad/SathyamurthySF98,
  author       = {Harsha Sathyamurthy and
                  Sachin S. Sapatnekar and
                  John P. Fishburn},
  title        = {Speeding up pipelined circuits through a combination of gate sizing
                  and clock skew optimization},
  journal      = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
  volume       = {17},
  number       = {2},
  pages        = {173--182},
  year         = {1998},
  url          = {https://doi.org/10.1109/43.681267},
  doi          = {10.1109/43.681267},
  timestamp    = {Thu, 24 Sep 2020 11:28:07 +0200},
  biburl       = {https://dblp.org/rec/journals/tcad/SathyamurthySF98.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
a service of  Schloss Dagstuhl - Leibniz Center for Informatics

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.