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"Speeding up pipelined circuits through a combination of gate sizing and ..."

Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn (1998)

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DOI: 10.1109/43.681267

access: closed

type: Journal Article

metadata version: 2020-09-24

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Harsha Sathyamurthy, Sachin S. Sapatnekar, John P. Fishburn:
Speeding up pipelined circuits through a combination of gate sizing and clock skew optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(2): 173-182 (1998)

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