default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID19th ARC 2023: Cottbus, Germany
- Francesca Palumbo, Georgios Keramidas, Nikolaos S. Voros, Pedro C. Diniz:
Applied Reconfigurable Computing. Architectures, Tools, and Applications - 19th International Symposium, ARC 2023, Cottbus, Germany, September 27-29, 2023, Proceedings. Lecture Notes in Computer Science 14251, Springer 2023, ISBN 978-3-031-42920-0
Design Methods and Tools
- Masayuki Usui, Shinya Takamaeda-Yamazaki:
High-Level Synthesis of Memory Systems for Decoupled Data Orchestration. 3-18 - Sara Sadat Hoseininasab
, Caroline Collange, Steven Derrien:
Rapid Prototyping of Complex Micro-architectures Through High-Level Synthesis. 19-34 - Sajjad Tamimi, Arthur Bernhardt, Florian Stock, Ilia Petrov, Andreas Koch:
NVMulator: A Configurable Open-Source Non-volatile Memory Emulator for FPGAs. 35-50 - Panagiotis Mousouliotis, Topi Leppänen, Pekka Jääskeläinen, Nikos Petrellis, Panagiotis Christakos, Georgios Keramidas, Christos P. Antonopoulos, Nikolaos S. Voros:
On the OpenCL Support for Streaming Fixed-Function Accelerators on Embedded SoC FPGAs. 51-65 - Jonas Gehrunger, Christian Hochberger:
Design Space Exploration of Application Specific Number Formats Targeting an FPGA Implementation of SPICE. 66-80 - Shaden M. Alismail, Dirk Koch:
Memory-Aware Scheduling for a Resource-Elastic FPGA Operating System. 81-96 - Lester Kalms, Matthias Nickel, Diana Göhringer:
ArcvaVX: OpenVX Framework for Adaptive Reconfigurable Computer Vision Architectures. 97-112
Applications
- Vitalii Burtsev, Martin Wilhelm, Anna Drewes, Bala Gurumurthy, David Broneske, Thilo Pionteck, Gunter Saake:
FPGA-Integrated Bag of Little Bootstraps Accelerator for Approximate Database Query Processing. 115-130 - José L. Núñez-Yáñez:
Accelerating Graph Neural Networks in Pytorch with HLS and Deep Dataflows. 131-145 - Srivatsan Chandrasekar, Siew-Kei Lam, Srikanthan Thambipillai:
DNN Model Theft Through Trojan Side-Channel on Edge FPGA Accelerator. 146-158 - Evangelia Konstantopoulou, George Athanasiou, Nicolas Sklavos:
Towards Secure and Efficient Multi-generation Cellular Communications: Multi-mode SNOW-3G/V ASIC and FPGA Implementations. 159-172 - Kai Lukas Unger, Jürgen Becker, Christian Kiesling, Yichuan Ma, Felix Meggendorfer, Marc Neu, Elia Schmidt, Ulrike Zweigart:
A Convolution Neural Network Based Displaced Vertex Trigger for the Belle II Experiment. 173-184 - Gianluca Leone, Luca Martis, Luigi Raffo, Paolo Meloni:
On-FPGA Spiking Neural Networks for Multi-variable End-to-End Neural Decoding. 185-199 - Maciej Baczmanski, Mateusz Wasala, Tomasz Kryjak:
Implementation of a Perception System for Autonomous Vehicles Using a Detection-Segmentation Network in SoC FPGA. 200-211
Architectures
- George Pagonis, Vasileios Leon, Dimitrios Soudris, George Lentaris:
Increasing the Fault Tolerance of COTS FPGAs in Space: SEU Mitigation Techniques on MPSoC. 215-229 - Rafael Fão de Moura, Luigi Carro:
Scalable and Energy-Efficient NN Acceleration with GPU-ReRAM Architecture. 230-244 - Lennart Clausing, Zakarya Guettatfi, Paul Kaufmann, Christian Lienen, Marco Platzner:
On Guaranteeing Schedulability of Periodic Real-Time Hardware Tasks Under ReconOS64. 245-259 - Andrés Otero, Guillermo Sanllorente, Eduardo de la Torre, José L. Núñez-Yáñez:
Evolutionary FPGA-Based Spiking Neural Networks for Continual Learning. 260-274 - Alexander Lehnert, Hans Rosenberger, Ralf R. Müller, Marc Reichenbach:
More Efficient CMMs on FPGAs: Instantiated Ternary Adders for Computation Coding. 275-289 - Bijin Elsa Baby, Dipika Deb, Benuraj Sharma, Kirthika Vijayakumar, Satyajit Das:
Energy Efficient DNN Compaction for Edge Deployment. 290-303
Special Session: Near and In-Memory Computing
- Johannes Knödtel, Hector Gerardo Muñoz Hernandez, Alexander Lehnert, Gia Bao Thieu, Sven Gesper, Guillermo Payá-Vayá, Marc Reichenbach:
TAPRE-HBM: Trace-Based Processor Rapid Emulation Using HBM on FPGAs. 307-321 - Philipp Grothe, Saleh Mulhem, Mladen Berekovic:
An Almost Fully RRAM-Based LUT Design for Reconfigurable Circuits. 322-337 - Takeshi Senoo, Ryota Kayanoma, Akira Jinguji, Hiroki Nakahara:
A Light-Weight Vision Transformer Toward Near Memory Computation on an FPGA. 338-353
PhD Forum Papers
- Eike Trumann, Gia Bao Thieu, Johannes Schmechel, Kirsten Weide-Zaage, Katharina Schmidt, Dorian Hagenah, Guillermo Payá Vayá:
Radiation Tolerant Reconfigurable Hardware Architecture Design Methodology. 357-360 - Daniele Passaretti, Thilo Pionteck:
A Control Data Acquisition System Architecture for MPSoC-FPGAs in Computed Tomography. 361-365 - Julian Haase, Diana Göhringer:
Simulation and Modelling for Network-on-Chip Based MPSoC. 366-370 - Safdar Mahmood, Michael Hübner, Marc Reichenbach:
A Design-Space Exploration Framework for Application-Specific Machine Learning Targeting Reconfigurable Computing. 371-374
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-12-05 22:23 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
