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ORCID10th IEEE Symposium on Computer Arithmetic 1991: Grenoble, France
- 10th IEEE Symposium on Computer Arithmetic, ARITH 1991, Grenoble, France, June 26-28, 1991. IEEE 1991, ISBN 0-8186-9151-4
- Jean Duprat, Yvan Herreros, Sylvanus Kla:
New redundant representations of complex numbers and vectors. 2-9 - Françoise Chaitin-Chatelin, Valérie Frayssé:
Analysis of arithmetic algorithms: a statistical study. 10-16 - Christiane Frougny:
Representation of numbers in nonclassical numeration systems. 17-21 - Gerd Bohlender, Wolfgang Walter, Peter Kornerup, David W. Matula:
Semantics for exact floating point operations. 22-26 - Michael S. Paterson, Uri Zwick:
Shallow multiplication circuits. 28-34 - Naofumi Takagi:
A radix-4 modular multiplication hardware algorithm efficient for iterative modular multiplications. 35-42 - Mayur Mehta, Vijay Parmar, Earl E. Swartzlander Jr.:
High-speed multiplier design using multi-input counter and compressor circuits. 43-50 - Holger Orup, Peter Kornerup:
A high-radix hardware algorithm for calculating the exponential ME modulo N. 51-56 - David Zhang, Graham A. Jullien, William C. Miller, Earl E. Swartzlander Jr.:
Arithmetic for digital neural networks. 58-63 - Michael Müller, Christine Rüb, Wolfgang Rülling:
Exact accumulation of floating-point numbers. 64-69 - Andreas Knöfel:
Fast hardware units for the computation of accurate dot products. 70-74 - Jen-Shiun Chiang, Mi Lu:
A general division algorithm for residue number systems. 76-83 - Dragan Gamberger:
New approach to integer division in residue number systems. 84-91 - Neil M. Wigley, Graham A. Jullien, Daniel Reaume, William C. Miller:
Small moduli replications in the MRRNS. 92-99 - Stanislaw J. Piestrak:
Design of residue generators and multioperand modular adders using carry-save adders. 100-107 - Hidetoshi Yokoo:
Overflow/underflow-free floating-point number representations with self-delimiting variable-length exponent field. 110-117 - Peter R. Turner:
Implementation and analysis of extended SLI operations. 118-126 - Thomas E. Hull, Marty S. Cohen, C. B. Hall:
Specifications for a variable-precision arithmetic coprocessor. 127-131 - Douglas M. Priest:
Algorithms for arbitrary precision floating point arithmetic. 132-143 - Vitit Kantabutra:
Designing optimum carry-skip adders. 146-153 - Pak K. Chan, Martine D. F. Schlag, Clark D. Thomborson, Vojin G. Oklobdzija:
Delay optimization of carry-skip adders and block carry-lookahead adders. 154-164 - Thomas W. Lynch
, Earl E. Swartzlander Jr.:
The redundant cell adder. 165-170 - Lars Kühnel:
Optimal purely systolic addition. 172-179 - Jean Vuillemin:
Constant time arbitrary length synchronous binary counters. 180-183 - Robert Alverson:
Integer division using reciprocals. 186-190 - Derek C. Wong, Michael J. Flynn:
Fast division using accurate quotient approximations to reduce the number of iterations. 191-201 - Paolo Montuschi, Luigi Ciminiera:
Simple radix 2 division and square root with skipping of some addition steps. 202-209 - Ted E. Williams, Mark A. Horowitz:
A 160 ns 54 bit CMOS division implementation using self-timing and symmetrically overlapped SRT stages. 210-217 - Shrikant N. Parikh, David W. Matula:
A redundant binary Euclidean GCD algorithm. 220-225 - Alain Guyot:
OCAPI: architecture of a VLSI coprocessor for the GCD and the extended GCD of large numbers. 226-231 - Ping Tak Peter Tang:
Table-lookup algorithms for elementary functions and their error analysis. 232-236 - Warren E. Ferguson, Tom Brightman:
Accurate and monotone approximations of some transcendental functions. 237-244 - Paul K.-G. Tu, Milos D. Ercegovac:
Application of on-line arithmetic algorithms to the SVD computation: preliminary results. 246-255 - Shen-Fu Hsiao, Jean-Marc Delosme:
The CORDIC Householder algorithm. 256-263 - Jeong-A Lee, Tomás Lang:
SVD by constant-factor-redundant-CORDIC. 264-271 - Alfons A. J. de Lange, Ed F. Deprettere:
Design and implementation of a floating-point quasi-systolic general purpose CORDIC rotator for high-rate parallel data and signal processing. 272-281
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