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ORCID29th ASYNC 2025: Portland, OR, USA
- 29th IEEE International Symposium on Asynchronous Circuits and Systems, ASYNC 2025, Portland, OR, USA, May 11-14, 2025. IEEE 2025, ISBN 979-8-3315-0310-9
- Xuanyu Zhang, Jilin Zhang, Haoyang Huang, Hong Chen:
An Asynchronous RISC-V-based SNN Processor with Custom ISA Extensions for Programmable On-Chip Learning. 1-8 - Jon Dama:
Scaledmatx One : A Bundled-Data GALS Inference ASIC. 9-12 - Andrew Lines, Ruokun Liu:
Mount Sisyphus: Energy-Efficient Asynchronous RISC-V Microcontroller in Intel 3 Process. 13-18 - Shengyu Duan
, Marcos L. L. Sartori, Rishad A. Shafik, Alex Yakovlev, Emre Ozer:
Efficient FPGA Implementation of Time-Domain Popcount for Low-Complexity Machine Learning. 19-27 - Giuseppe Chessa, Elena Bellodi, Michele Favalli, Davide Zoni, Davide Bertozzi:
A Synthesis Toolflow for the Predictable Implementation of High-Performance Bundled-Data Asynchronous NoCs on FPGA. 28-37 - Josef Salzmann:
Distributed Locally Synchronous Grid Oscillator via Perpetual Token Exchange. 38-45 - Robert Karmazin, Andrew Lines, Prasad Joshi, Benjamin Hill:
Clock Generator with Clock Domain Crossing. 46-55 - Philipp Lehninger, Axel Jantsch, Andreas Steininger, Elliott Worsey, Victor Marot, Dinesh Pamunuwa:
Muller C-Element for NEMS. 56-62 - Danil Sokolov, Victor Khomenko, Marco Sautto:
Easy async for busy engineers: AFSM-based design of low-latency robust controllers in Workcraft*. 63-64 - Cole Sherrill, Ethan Brugger, Jia Di:
Synthesis and Timing Constraints for Reliable MTNCL Asynchronous Circuits. 65-73 - Cole Sherrill, Kile Harvey, Zhihan Weng, Jia Di:
Innovations in MTNCL Gate Design: An Alternative MTCMOS Power-Gating Approach. 74-79 - Xiayuan Wen, Rui Li, Rajit Manohar:
Translating General Slack Elastic Programs into Dataflow Circuits. 80-88 - Hugh Squires-Parkin, Alex Chan, Rishad A. Shafik, Adrian Wheeldon, Alex Yakovlev:
Asynchronous Design of a Bitwise Elimination Argmax via High-Level Modeling in GraphRack. 89-98 - Karthi Srinivasan, Rajit Manohar:
Automated Decomposition of Concurrent Programs for Asynchronous Logic Synthesis. 99-107 - Leo Liu, Kwabena Boahen:
Hierarchical Event Readout with Asynchronous Pipelined Opportunistic Merges. 108-117 - Prafull Purohit, Rajit Manohar:
Asynchronous, event-driven readout for large-scale imaging devices. 118-125 - Dimitrios Tsalapatas, Nikolaos Chatzivangelis, Christos P. Sotiriou, Nikolaos Sketopoulos:
Post-Placement Timing Optimisations on Asynchronous Designs. 126-134 - Sumanth Kolluru, Kenneth S. Stevens:
Timing Closure in Relative Timed Asynchronous Designs using Deep Reinforcement Learning. 135-141 - Raghda El Shehaby, Matthias Függer, Florian Huemer, Andreas Steininger:
Investigating the Effects of Permanent Faults in QDI Circuits: A Formal Perspective. 142-150
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